SPEAR-09-H122

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Reference	Filesize	Pages	Last Updated
SPEAR-09-H122	324KB	40	Jul-2008

Device	Status	RoHS	Purchase
SPEAR-09-H122	Preview	Converted

	ARM926EJ-S core @ 333 MHz
	600 Kgates reconfigurable logic array with 88 dedicated general purpose I/Os, 9 LVDS channels and 128 Kbyte configurable internal memory pool
	Multilayer AMBA 2.0 compliant bus with fMAX 166 MHz
	32 Kbyte ROM, 8 Kbyte common static RAM
	Dynamic power saving features
	Color LCD controller
	JPEG codec accelerator
	Large set of connectivity IPs: - Ethernet MAC 10/100/1000 with GMII/MII protocol - 2 fully independent USB 2.0 hosts and one USB 2.0 device with embedded PHYs - 2 UARTs and I2C
	Interfaces for DDR1/DDR2 memories and Flash memories (NAND 8/16 bit and SPI serial NOR)

The SPEAr Head600 is a digital engine based on an ARM-based architecture and an embedded programmable logic block. The ARM926EJ-S processor (up to 333 MHz) eliminates the need to develop a complete RISC system, while the logic block (600 Kbyte) allows customers to introduce special functions and/or proprietary IPs.

As for the other members of the SPEAr family, the SPEAr Head600 guarantees interconnection to a great number of peripherals. In addition, the device offers new features, such as a color LCD controller (up to 1024 x 768 resolution) and a JPEG codec accelerator.

Reference	Filesize	Pages	Last Updated
SPEAR-09-H122	330KB	37	02/03/2007