SPEAR-09-P022

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Reference	Filesize	Pages	Last Updated
SPEAR-09-P022	328KB	40	Jul-2008

Device	Status	RoHS	Purchase
SPEAR-09-P022	Preview	Converted

	Dual ARM926EJ-S core @ 333 MHz
	600 Kgates reconfigurable logic array with 88 dedicated general purpose I/Os, 9 LVDS channels and 128 Kbyte configurable internal memory pool
	Multilayer AMBA 2.0 compliant bus with fMAX 166 MHz
	32 Kbyte ROM, 8 Kbyte common static RAM
	Dynamic power saving features
	Color LCD controller
	JPEG codec accelerator
	Large set of connectivity IPs: - Ethernet MAC 10/100/1000 with GMII/MII protocol - 2 fully independent USB 2.0 hosts and one USB 2.0 device with embedded PHYs - 2 UARTs and I2C
	Interfaces for DDR1/DDR2 memories and Flash memories (NAND 8/16 bit and SPI serial NOR)

The SPEAr Plus600 combines the benefits of the SPEAr Head600 digital engine with higher performance computing, since it is based on a dual core ARM architecture. The device integrates a dual ARM926EJ-S processor and an embedded programmable logic block.

The fully symmetric processor architecture generates many advantages:
- All internal peripherals are shared, allowing flexible and efficient SW partitions
- High throughput can be sustained in an aggregate way sharing critical tasks on additional CPUs and optional HW accelerator engines
- Critical resources are private to each CPU (interrupt controller and OS timers)
- Both processors are equipped with ICE and ETM configurable debug interfaces

Reference	Filesize	Pages	Last Updated
SPEAR-09-P022	330KB	37	02/03/2007