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IMPORTANT NOTICE
Dear customer, As from August 2nd 2008, the wireless operations of STMicroelectronics have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document.
Company name - STMicroelectronics NV is replaced with ST-NXP Wireless. Copyright - the copyright notice at the bottom of the last page " STMicroelectronics 200x - All rights reserved", shall now read: " ST-NXP Wireless 200x - All rights reserved". Web site - http://www.st.com is replaced with http://www.stnwireless.com Contact information - the list of sales offices is found at http://www.stnwireless.com under Contacts.
If you have any questions related to the document, please contact our nearest sales office. Thank you for your cooperation and understanding. ST-NXP Wireless
ww.stnwireless.com
STw4811M STw4811N
Power management for multimedia processors
Features
2 step-down converters 1 to 1.45 V with 15 steps at 700 mA 1.8 V at 600 mA for general purpose usage 3 low-drop output regulators for different uses PLL analog supplies: 1.05 V, 1.2 V, 1.3 V 1.8 V - 10 mA Processor analog functions: 2.5 V - 10 mA Auxiliary device: 1.5 V, 1.8V , 2.5 V, 2.8 V - 150 mA USB OTG module Full and low speed USB OTG transceiver Charge-pump (5 V, 100 mA) for USB cable Mass memory cards (SD/MMC/SDIO) 1 linear regulator: 1.8 V, 1.85 V, 2.6 V, 2.7 V, 2.85 V, 3 V, 3.3 V - 150 mA Level shifter Miscellaneous 32 kHz control for multimedia processor Processor supply monitoring Processor reset control 2 serial I2C interfaces
STw4811 TFBGA 84 6x6x1.2mm 0.5mm pitch STw4811 VFBGA 84 4.6x4.6x1.0mm 0.4mm pitch
Description
STw4811 is a power management companion chip for multimedia processors used in portable applications. It supplies the multimedia processor including its memories and peripherals. STw4811 supports the main mass memory standard cards. SDIOTM is also supported and allows to connect multimedia peripherals like cameras.
Appl ication s
ST NomadikTM STn881x Multimedia processor Mobile phones, PDA, videophone
August 2008
Rev 3
1/85
www.stnwireless.com
1
Contents
STw4811M/STw4811N
ontents
1 2 3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ball information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3. 2 Ball connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Ball functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Digital control module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 State machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 POWER OFF / VDDOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 IT generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Clock switching and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.3
Power management module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9 Bandgap, biasing and references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 VCORE regulator: DC/DC STEP- DOWN regulator . . . . . . . . . . . . . . . 41 VIO_VMEM regulator: DC/DC step- down regulator . . . . . . . . . . . . . . . 41 VPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 VAUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Power supply domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Thermal shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.4
USB OTG module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4.1 4.4.2 4.4.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Modes and operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 USB enable control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.5
SD/MMC/SDIO module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.5.1 SD/MMC/SDIO LDO supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2/85 C
Tw4811M/STw4811N 4.5.2
Contents Level shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5
Electrical and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5. 1 5. 2 5.3 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Package dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 VREF18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 VCORE DC/DC step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . 58 VIO_VMEM DC/DC step-down converter . . . . . . . . . . . . . . . . . . . . . . . 59 LDO regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5. 4
Digital specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 CMOS input/output static characteristics: I2C interface . . . . . . . . . . . . . 64 CMOS input/output dynamic characteristics: I2C interface . . . . . . . . . . 65 CMOS input/output static characteristics: VIO level . . . . . . . . . . . . . . . 66 CMOS input/output static characteristics: VBAT level . . . . . . . . . . . . . . . 68 CMOS input/output static characteristics: VMMC level . . . . . . . . . . . . . 69
5.5 5. 6
USB OTG transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SD/MMC/SDIO card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.1 6. 2 Components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7. 1 7. 2 TFBGA 84 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 VFBGA 84 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8 9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
S
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List of tables
STw4811M/STw4811N
ist of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. STw4811 ball connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 STw4811 balls function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Register address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Register data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Register general information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 USB register address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Vendor ID and Product ID: Read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 USB control register 1 (address = 04h set and 05h clearh) . . . . . . . . . . . . . . . . . . . . . . . . 25 USB control register 2 (address = 06h set and 07h clearh) . . . . . . . . . . . . . . . . . . . . . . . . 26 USB Interrupt source register (address = 08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 USB interrupt latch registers (address = 0Ah set and 0Bh clearh) . . . . . . . . . . . . . . . . . . . 27 USB interrupt enable low register (address = 0Ch and 0Dh) . . . . . . . . . . . . . . . . . . . . . . . 28 USB interrupt enable high register (address = 0Eh and 0Fh). . . . . . . . . . . . . . . . . . . . . . . 28 USB EN register (address = 10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Configuration 1 register (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power control register - General information (address = 1Eh) . . . . . . . . . . . . . . . . . . . . . . 31 Power control register - General information (address = 1Fh) . . . . . . . . . . . . . . . . . . . . . . 31 Power control register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power control register at address 05h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Power control register at address 06h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Power control register at address 07h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Power control register at address 08h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Power control register at address 09h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Power control register at address 0Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Configuration 2 register at address = 20h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 VCORE_sleep register at address = 21h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Power supply domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Thermal threshold values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 0 . . . . . . . . 48 Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 1 . . . . . . . . 49 Data receiver via USB control register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 STw4811 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Package dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Operating conditions (temperature range: -30 to +85 C). . . . . . . . . . . . . . . . . . . . . . . . . . 57 VREF18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 VCORE DC/DC step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 VIO_VMEM DC/DC step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 LDO regulators - VPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 LDO regulators - VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 LDO regulators - VAUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 CMOS input/output static characteristics: I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 CMOS input/output dynamic characteristics: I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . 65 VIO level: USB and control I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 VIO level: MMC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4/85 L
Tw4811M/STw4811N Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 56. Table 57. Table 58. Table 59.
List of tables
CMOS input/output static characteristics: VBAT level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 CMOS input/output static characteristics VMMC level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 USB OTG transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SD/MMC/SDIO card interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Recommended coils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch dimensions . . . . . . . . . . . . . . . . . . 79 VFBGA 84 balls / 4.6x4.6x1.0 mm body size / 0.4 mm ball pitch . . . . . . . . . . . . . . . . . . . . 81 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
S
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List of figures
STw4811M/STw4811N
ist of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Typical mobile multimedia system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 STw4811 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Start-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Switching power to sleep timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 VDDOK block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 I2C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Control interface: I2C format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Control interface: I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clock switching between master and internal clock (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Block diagram of biasing and references of the device . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 `vcore_available' bit behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Thermal threshold temperatures for `it_warn' bit and VDDOK ball . . . . . . . . . . . . . . . . . . . 45 USB OTG transceiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 SD/MMC/SDIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Propagation and clock/data skew times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 STw4811 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing . . . . . . . . . . . . . . . . . . . . . 80 VFBGA 84 balls 4.6x4.6x1.0 mm ball pitch 0.4 drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6/85 L
Tw4811M/STw4811N
Overview
1
Overview
The STw4811 power management device has the following features:
Power management module 1 step-down converter for processor core (1 V to 1.45 V with 15 steps at 700 mA) 1 step-down converter (1.8 V at 600 mA) for general purpose usage such as processor input/output supply, external memory, DDR and SDRAM and peripherals 1 low-drop output regulator for analog supplies, such as PLL (1.05 V, 1.2 V, 1.3 V, 1.8 V at 10 mA) 1 low-drop output regulator for processor analog functions (2.5 V at 10 mA) 1 low-drop output regulator for auxiliary devices (1.5 V, 1.8 V, 2.5 V, 2.8 V at 150 mA) STw4811M: Vaux OFF at start up STw4811N: Vaux ON at start up Full and low speed USB OTG transceiver 1 linear regulator 3.1 V supplying transceiver 1 charge-pump (5 V at 100 mA) supplying VBUS line of the USB cable 1 linear regulator (1.8 V, 1.85 V, 2.6 V, 2.7 V, 2.85 V, 3 V, 3.3 V at 150 mA) Level shifters 32 kHz control for multimedia processor Processor supply monitoring Processor reset control 2 serial I2C interfaces
Auxiliary device
USB OTG module
Mass memory cards (SD/MMC/SDIO)
Miscellaneous
S
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Overview igure 1. Typical mobile multimedia system
STw4811M/STw4811N
1
STw4811
8/85
F
Tw4811M/STw4811N
Functional block diagram
2
Figure 2.
Functional block diagram
STw4811 block diagram
V B A T _ V IO _ V M E M V IO _ V M E M VBAT_V C O R E VLX_VC O R E VCORE V M IN U S _ V C O R E V L X _ V IO _ V M E M V M IN U S _ V I O _ V M E M
V B A T _ D IG V M IN U S _ D IG
V IO _ V M E M STEP DOW N IN T E R N A L O S C IL L A T O R C L O C K S W IT C H IN G & CONTROL SOFT START
VCORE STEP DOW N
V BAT_AN A V M IN U S _ A N A
M AS TER _C LK C L K 3 2 K _ IN C LK 32K
REFERENCE V O LTAG E VP LL LDO 1 .0 5 , 1 .2 , 1 . 3 , 1 .8 V THERMAL SHUTDOW N 10 m A V AN A LD O 2 .5 V / 1 0 m A V AU X LD O 1 .5 , 1 .8 , 2 .5 , 2 .8 V 150 m A
V R EF_18
V PLL V BAT_VP LL_VAN A
TC XO _E N R E Q U E ST_M C PON VDDOK PORn PW REN SW RESETn GPO1 GPO2 U S B IN T n IT _ W A K E _ U P
VANA
GENERAL CONTROL
SUPPLY M O N IT O R IN G PORn VBAT
V BAT_VA U X VAUX
USB CONTROL I2 C IN T E R F A C E US B O TG tra n s c e iv e r I2 C
STw 4811
CP
CHARGE PUMP 5 V / 100 m A
CN VBUS V BAT_U SB
SDA SCL USBSDA USBSCL USBOEn USBVP USBVM USBRCV V M IN U S _ U S B M C C M D D IR M C D A T 0 D IR M C D A T 2 D IR M C D A T 3 1 D IR M C FBC LK M C C LK MCCMD MCDATA0 MCDATA1 MCDATA2 MCDATA3
MUX
CONTROL VUSB 3 .1 V
ID VUSB
D R IV E R S & LEV EL S H IF T E R S P ULL U P & PULL DOW N
DP DN
VMMC CONTROL 1 .8 , 1 .8 5 , 2 . 6 , 2 .7 2 .8 5 , 3 , 3 .3 V 150 m A
VBAT_M M C VMMC
LATC H C LK C LKO U T CMDOUT
LEVEL S H IF T E R S
DATA0 DATA1 DATA2 DATA3
S D /M M C I N T E R F A C E
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Ball information
STw4811M/STw4811N
Ball information
3.1
Table 1.
1 A B C D E F G H J K
CLK32K_IN
Ball connections
STw4811 ball connections
2
VMINUS_ VIO_VMEM
3
VLX_VIO_ VMEM
4
5
6
VAUX VBAT_ VAUX VBAT_ANA
7
VANA
8
VPLL
9
VREF_18
10
VCORE VMINUS_ VCORE VLX_ VCORE VBAT_ VCORE DN VUSB VBUS CP CN "Reserved"
VBAT_VIO_ VIO_VMEM VMEM VMINUS_ ANA "Reserved"
"Reserved" TCXO_EN VBAT_DIG DATAOUT0 DATAOUT <3> CLKOUT MCCMD MCDATA <2> MCDATA0
REQUEST_ VMINUS_ VBAT_VIO_ MC VIO_VMEM VMEM IT_WAKE_ UP MASTER_ CL K DATAOUT <1> CM DOUT MCCLK MCDATA <3> VDDO K MCDAT0 DIR VMINUS_ DI G "reserved" DATAOUT <2> LATCHCLK MCCMD DIR MCDATA <1> PORN CLK32K MCDATA31 DIR VBAT_ MMC SW_ RESET VLX_VIO_ VMEM
"Reserved" VBAT_ VPLL_ANA
"Reserved" PON VLX_ V C O RE ID "Reserved" "Reserved"
"Reserved" VMINUS_ VCORE VBAT_ VCORE DP VBAT_USB USBSCL USBSDA VMINUS_ USB MCDAT2 DIR
MCFBCLK GPO1 VMMC
PWREN SCL GPO2
SDA USBVP USBRCV
USBINTn USBVM USBOEn
3.2
Ball functions
STw4811 includes the following ball types
VDDD/VDDA: digital/analog power supply VSSD/VSSA: digital/analog ground supply DO/DI/DIO: digital output / digital input / digital input output DOz: digital output with high impedance capability AO/AI/AIO: analog output / analog input / analog input-output G: to be connected to ground O: to be left open Int-Ref: associated to internal reference
Table 2 details the ballout.
10/85 3
Tw4811M/STw4811N Table 2.
Ball General supplies D1 C3 C6 B5 F9 J9 A9 VBAT_DIG VMINUS_DIG VBAT_ANA VMINUS_ANA VBAT_USB VMINUS_USB VREF_18 VDDD-VBAT VSSD VDDA-VBAT VSSA VDDA-VBAT VSSA Int-Ref
Ball information
STw4811 balls function
Ball name Ball type Description
Batter y supply for digital/oscillator Ground for digital and oscillator Batter y supply for analog Ground for analog Batter y supply for USB block Ground for USB block Internal reference
Control balls C8 PON DI(VBAT) Pull down 1.5M DI(VIO_VMEM) Pull up 1.5M DO(VIO_VMEM) DO(VIO_VMEM) DI(VIO_VMEM) Pull Up 1.5M DI(VIO_VMEM) Pull Down 1.5M DO(VIO_VMEM) DI(VIO_VMEM) DIO(VIO_VMEM) AI Pull Down 1.5M DI(VIO_VMEM) Pull down 1.5M DO(VIO_VMEM) Power-on and reset Software reset. Reset all registers except power control and configuration 2 (address 20h) registers when SW_RESETn = 0 Supply monitoring for multimedia processors. Interruption for high temperature warning Multimedia processor Resetn Sleep mode from multimedia processor Request of master clock from modem part Request to master clock oscillator Clock for Main I2C interface SDA for Main I2C interface 26 MHz, 13 MHz or 19.2 MHz from modem 32 kHz input 32 kHz to multimedia processor
K4
SW_RESETn
J2 J3 H6 C1 B2 J6 H7 D2 A1 K3
VDDOK PORn PWREN TCXO_EN REQUEST_MC SCL SDA MASTER_CLK CLK32K_IN CLK32K
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Ball information Table 2.
Ball General supplies egulator balls A4 B4 A2 B3 A3 C4 A5 D9 D10 B10 C9 C10 D8 A10 C7 A7 A8 A6 B6 USB balls C2 K8 IT_WAKE_UP USBOEn DO (Open drain) DIO(VIO_VMEM) Pull down 1.5M DIO(VIO_VMEM) Pull down 1.5M DIO(VIO_VMEM) Pull Down 1.5M DO(VIO_VMEM) AIO(VUSB) AIO(VUSB) AI(VBAT-USB) VBAT_VIO_VMEM VMINUS_VIO_VMEM VLX_VIO_VMEM VIO_VMEM VBAT_VCORE VMINUS_VCORE VLX_VCORE VCORE VBAT_VPLL_ANA VANA VPLL VAUX VBAT_VAUX VDDA-VBAT VSSA AIO AI VDDA-VBAT VSSA AIO AI VDDA-VBAT AO AO AO VDDA-VBAT
STw4811M/STw4811N
STw4811 balls function (continued)
Ball name Ball type Description
Batter y power supply for step down VIO_VMEM Ground for step down VIO_VMEM BUCK of step down VIO_VMEM VIO_VMEM Feed back input Batter y power supply for step down VCORE Ground for step down VCORE BUCK of step-down VCORE VCORE sense Batter y supply for VPLL, VANA VANA output VPLL output VAUX output Batter y supply for VAUX
Interrupt to modem or APE for wake-up due to USB plug Output enable of the differential driver in the USB mode Data input in the USB transmit mode, positive data input the single-ended transmit mode, or TXD in UART mode Single-ended zero input in the USB transmit mode, negative data input in the single-ended transmit mode, or RXD in the UART mode Differential receiver output Positive data line in the USB mode, or serial data input in the UART mode Negative data line in the USB mode, or serial data output in the UART mode. ID ball of the USB detector used for protocol identification.
J7
USBVP
J8 K7 E9 E10 E8
USBVM USBRCV DP DN ID
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Tw4811M/STw4811N Table 2.
Ball General supplies H10 J10 G10 F10 G9 H9 H8 CP CN VBUS VUSB USBSCL USBSDA USBINTn AIO(VBUS) AIO(VBUS) AIO(VBUS) AIO DI(VIO_VMEM) DIO(VIO_VMEM) DO(VIO_VMEM) C plus flying capacitor (VBUS level 4.4 to 5.25)
Ball information
STw4811 balls function (continued)
Ball name Ball type Description
C minus flying capacitor (VBUS Level) USB cable supply (VBUS Level) Decoupling capacitor for USB internal regulator Clock for dedicated USB I2C SDA for dedicated USB I2C Interrupt to multimedia processor for USB or accessory plug
SD/MMC/SDIO balls G3 MCCMDDIR DI(VIO_VMEM) Pull down 1.5M DI(VIO_VMEM) Pull down 1.5M DI(VIO_VMEM) Pull down 1.5M CMD direction. - "high": CMD signal from processor to card - "Low": CMD signal from card to processor DATA0 direction - "high": DATA0 signal from processor to card - "Low": DATA0 signal from card to processor DATA2 direction - "high": DATA2 signal from processor to card - "Low": DATA2 signal from card to processor DATA(3,1) direction - "high": DATA(3,1) signal from processor to card - "Low": DATA(3,1) signal from card to processor Host clock, between processor and STw4811, to the card (processor clock). Host feedback clock between STw4811 and processor, to re-synchronize data in processor. Bidirectional command/response signal between processor and STw4811. Bidirectional data0 between processor and STw4811 Bidirectional data [3:1] between processor and STw4811. Host feedback clock to STw4811, to resynchronize data in processor. Host clock, between STw4811 and card (processor clock). Bidirectional command/response signal between STw4811 and processor.
K2
MCDAT0DIR
K9
MCDAT2DIR
H4
MCDAT31DIR
DI(VIO_VMEM) Pull down 1.5M
G2 H5 H1 K1 H2 H3 J1 F3 G1 F2
MCCLK MCFBCLK MCCMD MCDATA0
DI(VIO_VMEM) Pull Down 1.5M DO(VIO_VMEM) DIO(VIO_VMEM) Pull Up 1.5M DIO(VIO_VMEM) Pull Up1.5M DIO(VIO_VMEM) Pull up 1.5M DI(VMMC) Pull down 1.5M DO(VMMC) DIO(VMMC) Pull up 1.5M
MCDATA[3:1]
LATCHCLK CLKOUT CMDOUT
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Ball information Table 2.
Ball General supplies 1 F1 E3 E2 J4 K5 Other balls J5 K6 B9 D3 B1 B7 B8 C5 F8 G8 K10 GPO1 GPO2 "Reserved" AO AO G DATAOUT0 DIO(VMMC) Pull up 1.5M DIO(VMMC) Pull up 1.5M VDDA-VBAT AIO
STw4811M/STw4811N
STw4811 balls function (continued)
Ball name Ball type Description
Bidirectional data0 between STw4811 and card Bidirectional data[3:1] between STw4811 and card. Batter y supply for VMMC VMMC supply output
DATAOUT[3:1] VBAT_MMC VMMC
General purpose output General purpose output To be connected to ground
"Reserved"
O
To be left open
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Tw4811M/STw4811N
Functional description
4
4.1
Functional description
Introduction
The STw4811 integrates all the power supplies for a multimedia processor as well as memories and peripherals:
Two switched mode power supply regulators: one for the multimedia processor core, one for multimedia processor I/Os and memories Three low-drop output regulators for multimedia processor analog supplies (PLL and others) and auxiliary components USB OTG FS/LS physical interface MMC card power supplies and level shifters Multimedia processor supply monitoring / power-on reset and power supply alarms / interrupt management Two serial I2C communication interfaces; one to control the devices (SDA, SCL) and one to control the USB (USBSDA, USBSCL).
4.2
Digital control module
This module describes the interfaces used to program the device and the related registers.
4.2.1
State machine
Description of each states: (Figure 3.) OFF: In this mode the STw4811 is switched off. Off is when PON=0, when battery level is under 2.4 V or when thermal shutdown is activated. There is no multimedia processor power supply. The only active cell is the USB cable detection and VBAT level detection. OSC_START: Oscillator is enabled and the power up module is waiting for the rising edge of the internal signal OSC_OK to start power up sequence. This state duration is 300 s. START_BIAS: Bias, reference and thermal shut-down are enabled, a counter is activated to wait for rising edge of internal signals PDN_regulators. This state duration has a typical value of 7.77 ms and a worst case value of 9.46 ms. START_PM: after a 1 ms wait, multimedia processor power supplies are available (VIO_VMEM, VCORE, VPLL, and VANA). The device can allow I2C communication, output power supply monitoring and application (USB,SD/MMC/SDIO). OFF2: STw4811 is waiting for the 32 kHz multimedia processor signal. This state has an indeterminate duration. If 32kHz is present during the states describes above, it has no effect. The 32 kHz signal is taken into account by STw4811 only when the `VDDOK' ball is high, that is at the end of START_PM state. RESET: STw4811 forces a reset during 11*1/32 kHz period before setting PORn high. INT_OSC: The STw4811 can work without MASTER_CLK via its internal oscillator. The device waits for an external clock detection before switching to the external clock. When receiving a rising edge on PWREN ball (coming from multimedia processor) or on TCXO_EN ball (coming from modem), STw4811 answers by asserting to "1" the
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15/85
Functional description
STw4811M/STw4811N
EQUEST_MC ball. STw4811 remains in internal oscillator mode until it receives the external clock signal on MASTER_CLK ball (optional). EXT_CLK: if MASTER_CLK is used, when detected, the STw4811 uses this clock as reference and switches off its internal oscillator. MASTERCLK should remain connected up to sleep mode. SLEEP: sleep mode is required by multimedia processor by setting a PWREN at low level. Then VDDOK is forced to 0, regulators (VCORE, VIO_VMEM) switch to sleep mode and wait for PWREN at high level (Figure 4). WAKE-UP: from sleep mode, the multimedia processor requests to switch back to high power mode. Thus the device restarts its internal oscillator and then switches regulators from SLEEP to high power mode and informs multimedia processor with VDDOK at high level (Figure 4).
Note:
The default state of VAUX is different for STw4811M and for STw4811N. - VAUX default state is OFF at start up for STw4811M. - VAUX default state is ON at start up for STw4811N. VAUX can be programmed in high power mode only by asserted pdn_vaux bit to "1" (Table 18). If MASTER_CLK is used instead of internal oscillator all the features are not supported in sleep mode (see Section 4.2.3).
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R
Tw4811M/STw4811N Figure 3. Start-up timing
OFF VBAT
Functional description
PON ball
300s
9.38ms (11ms wc)
PDN__OSC PDN_regulators VDDOK ball
11*(1/32kHz) START_BIAS 7.77ms (9.46ms wc) START_PM 1ms
CLK32K_IN ball PORn ball PWREN ball
(*) Reset
Internal_OSC MASTER_CLK ball TCXO_EN ball REQUEST_MC ball
OFF2 VPLL / VIO_VMEM VCORE Reset "or" INT_OSC
Voutput(s) ball
CLK32K ball Delays are worst case maximum delays (*) If 32 kHz available before VDDOK signal rising edge, OFF2 state duration is null
All regulators are started with PDN_regulators or EN_regulators but can be switched off from the beginning or during application by software, `pdn_(regulator)' or `en_(regulator)' bits (Table 18,Table 24, and Table 25).
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Functional description igure 4. Switching power to sleep timing
HPM PWREN Sleep regulators VDDOK PDN_regulators CLK32K PDN_intOSC int_OSC _detect REQUEST_MC Inter nal_OSC MA ST ER _C LK TCXO_EN "0" Sleep ~100s
STw4811M/STw4811N
HP M
Register reset
In the event of a hardware reset coming from the modem, PON ball set to "0", all registers are reset at initial value when PON ball goes back to "1" level. A software reset from multimedia processor of STw4811, through SW_RESETn ball set to "0", resets all registers except power control register (at address 1E & 1F) and the configuration 2 register at address 20h.
Main clock oscillator control
REQUEST_MC is an OR output gate between PWREN (coming from multimedia processor) and TCXO_EN (coming from modem supply), it is synchronized on 32 kHz, except during power-up where PWREN is masked and considered as high. REQUEST_MC enabled or disabled the master clock oscillator device.
18/85
F
Tw4811M/STw4811N
Functional description
4.2.2
POWER OFF / VDDOK
In case of VDDOK falling edge due to under voltage on VCORE or VIO_VMEM detection, or `it_twarn' bit set to "1" (Table 18); the multimedia processor is then reset (PORn low during a minimum time of 333 s) and restarted with no time-out. (see Figure 5). In case of VDDOK falling edge because PWREN balls equals "0", there is no reset (PORn still high). In case of PON falling edge (STw4811 switched off from modem); the multimedia processor is also reset with no time-out. We consider that clean switch off between modem and multimedia processor is done by software directly. VDDOK block diagram
Figure 5.
Digital block PWREN & VDDOK
it_twarn mask_twarn register reset after read operation or PON falling edge or PORN_VBAT.
Reg status
4.2.3
Sleep mode
STw4811 goes into sleep mode by different ways. Whether VCORE, VIO_VMEM and VAUX are programmed to sleep mode or not is indicated in Table 26 and Table 27. Taking in account the bit programming from Table 26 and Table 27, sleep mode is summarized with the following formula: SLEEP = (`vxxx_sleep' x PWREN) + (`vxxx_force_sleep') = 1 (vxxx = vcore or vio_vmem or vaux)
Note:
The configuration vxxx_sleep = 0 (device in active mode) and vxxx_force_sleep = 1 (device in sleep mode, but no priority level on this bit) is forbidden.
If the master clock is used in high power mode when switching to sleep mode, the following features are not available: Bit 1 (vcore_sleep) and bit 2 (vio_vmem_sleep) in power control register address 9 must be at high level (VIO_VMEM and VCORE cannot remain in high power mode) USB charge pump is not available in sleep mode: bit 5 in USB control register address 07h must be set
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19/85
Functional description
STw4811M/STw4811N
.2 . 4
I2C Interface
The device supports two I2C bus interfaces. One main interface (SDA,SCL) controls power management and all programmable functions, the second interface (USBSDA, USBSCL) is dedicated to USB control. STw4811 allows to work with only the main I2C interface to control all the functions, including the USB, via `usb_i2c_ctrl' bit of power control register (Table 23). I2C interface is used to read status information from inside the device.
Flags, interrupt and write registers are used to configure the device functions (threshold, clock division, output voltage, etc....). By default, the main I2C interface (SCL,SDA) controls the main registers and USB I2C interface (USBSCL, USBSDA) controls USB registers.
Figure 6. I2C interface block diagram
SCL SDA usb_i2c_ctrl SCL MUX SDA USBSCL USBSDA
Main registers
SCL or USBSCL SDA or USBSDA USB registers
Both I2C are configured as slave serial interface compatible with I2C registered trademark of Phillips Inc. (version 2.1).
I2C interface description
Note: When not using the USB I2C interface, the two pins USBSCL and USCSDA must be connected to the VIO voltage.
STw4811 I2C is a slave serial interface with a serial data line (SDA or USBSDA) and a serial clock line (SCL or USBSCL):
SCL / USBSCL: input clock used to shift data SDA / USBSDA: input/output bidirectional data transfers One filter to reject spikes on the bus data line and preserve data integrity Bidirectional data transfers up to 400kbit/s (fast mode) via SDA or USBSDA signal
It is composed of:
The SDA or USBSDA signal contains the input/output control and data signals that are shifted in the device, MSB first. The first bit must be high (START) followed by the Device ID (7 bits) and Read/Write bit control (1 indicates read access, a logical 0 indicates a write access).
Device ID in write mode: 5Ah (01011010) Device ID in read mode: 5Bh (01011011)
Then STw4811 sends an acknowledge at the end of an 8 bit transfer. The next 8 bits correspond to the register address followed by another acknowledge. The 8-bit data field is sent last, followed by a last acknowledge.
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Tw4811M/STw4811N Table 3.
b7 AdrID6
Functional description
Device ID
b6 AdrID5 b5 AdrID4 b4 AdrID3 b3 AdrID2 b2 AdrID1 b1 AdrID0 b0 R/W
Table 4.
b7 RegADR7
Register address
b6 RegADR6 b5 RegADR5 b4 RegADR4 b3 RegADR3 b2 RegADR2 b1 RegADR1 b0 RegADR0
Table 5.
b7 DATA7
Register data
b6 DATA6 b5 DATA5 b4 DATA4 b3 DATA3 b2 DATA2 b1 DATA1 b0 DATA0
I2C interface modes
Figure 7. Control interface: I2C format
DEVICE ADDRESS ACK ACK REGn ADDRESS REGn Data In ACK
WRITE SINGLE BYTE
01011010
START DEVICE ADDRESS ACK ACK REGn ADDRESS REGn Data In ACK STOP ACK REGn+m Data In STOP m+1 data bytes ACK
WRITE MULTI BYTE
01011010
START
RANDOM ADDR READ SINGLE BYTE
DEVICE ADDRESS
ACK ACK REGn ADDRESS
DEVICE ADDRESS
ACK REGn Data Out
NO ACK
01011010
START
01011011
START
RANDOM ADDR READ MULTI BYTE DEVICE ADDRESS ACK ACK REGn ADDRESS ACK DEVICE ADDRESS ACK Reg n Data Out ACK
01011010
START
01011011
START m+1 data bytes
NO ACK Reg n + m Data Out STOP
Figure 8.
Control interface: I2C timing
SDA USBSDA SCL USBSCL
Stop
tbuf thd_sta tf tlow tr thigh thd_dat tsu_dat
tsu_sta thd_sta tsu_sto
Start
Start repeated
Stop
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21/85
Functional description
STw4811M/STw4811N
.2 .5
Control registers
Control registers have the following functions:
select level of regulation for multimedia processor supply control the USB interface control the SD/MMC/SDIO interface control the state machine
Table 6.
Register general information
Comment I2C control USBSDA / USBSCL or SDA / SCL (1) SDA / SCL
Address 00h to 10h 11h 12h to 1Dh 1Eh to 1Fh 20h 21h
USB registers (Table 9 to Table 17) Configuration 1 register (Table 18)
Reser ved registers
Power control registers (Table 19 to Table 27) Configuration 2 register (Table 28)
VCORE_sleep (Table 29)
SDA / SCL SDA / SCL SDA/SCL
1. Controlled by USB_I2C_CTRL bit of power control register (Table 23)
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Tw4811M/STw4811N
Functional description
Register summary
Table 7.
Register Vendor ID 01h 02h Product ID 03h USB control register 1 USB control register 2 USB interrupt source USB interrupt latch USB interrupt mask false USB interrupt mask true USB EN 04h 05h 06h 07h 08h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 0 1 0 oe_int_en vbus_ dr v id_float id_float id_float id_float Not used 0 bdis_ acon_en id_gnd dn_hi dn_hi dn_hi dn_hi 0 not used 0 dat_se0 0 suspend 0 speed dp_ pullup vbus_vld vbus_vld vbus_vld vbus_vld not used 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1
Register summary
Addr. 00h 7 1 6 0 5 0 4 0 3 0 2 0 1 1 0 1
Not used uar t_en vbus_ chrg cr_int cr_int cr_int cr_int Not used vbus_ dischrg bdis_ acon bdis_ acon bdis_ acon bdis_ acon B_sess_ end
dn_ dp_ dn_ pulldown pulldown pullup id_gnd_ forced id_gnd_ forced id_gnd_ forced id_gnd_ forced dp_hi dp_hi dp_hi dp_hi th_ Bdevice sess_vld sess_vld sess_vld sess_vld usb_en
Configuration 1
11h
pdn_ vaux
it_warn
monitoring _vio_ mmc_ls_ vmmc_sel[2:0] vmem_ status vcore not used gpo2 vcore_ available gpo1
pdn_ vmmc
Configuration 2 Vcore_Sleep
20h 21h
not used not used
mask_it_ external_ mask_ twarn wake_up vmmc
vcore_sleep[3:0]
Table 8.
Addr. 1Fh Addr. 1 Eh
Power control register
15 14 13 12 11 10 9 8
Not used 7 6 reg address 3 bits 5 4 3 2
reg address 2 bits 1 0 ena write
data din/dout 4 bits
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Functional description
STw4811M/STw4811N
egisters controlled by I2C USB bus
The registers described in this chapter are controlled through the USB serial I2C interface, USBSCL and USBSDA balls. These registers can also be controlled through the main I2C interface, SCL and SDA balls by setting to "1" `usb_i2c_ctrl' bit in power control register (Table 23). Table 9. USB register address
Register Vendor ID Product ID USB control register 1 USB control register 1 USB control register 2 USB control register 2 USB interrupt source Not used USB interrupt latch USB interrupt latch USB interrupt mask false USB interrupt mask false USB interrupt mask true USB interrupt mask true USB_EN R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R Type
Address 00h - 01h 02h - 03h 04h set 05h clearh 06h set 07h clearh 08h 09h 0Ah set 0Bh clearh 0Ch set 0Dh clearh 0Eh set 0Fh clearh 10h
Note:
A bit of register 1 is set at "1" by writing a "1" at address 04h, is reset at "0" by writing a "1" at address 05h. This is also applicable for USB control register 2 (06h, 07h), USB interrupt register (0Ah,0Bh), USB interrupt mask false register (0Ch, 0Dh) and USB interrupt mask true register (0Eh, 0Fh). Writing "0" at any address has not effect on the content of any register.
Table 10. Vendor ID and Product ID: Read only
Name Vendor ID Vendor ID Product ID 03h 40h Address 00h 01h 02h Register value 83h 04h 11h
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Tw4811M/STw4811N
Functional description
USB control register 1
Table 11.
7 Not used -
USB control register 1 (address = 04h set and 05h clearh)
6 uar t_en R/W 5 oe_int_en R/W 4 bdis_ acon_en R/W 3 not used 2 dat_se0 R/W 1 suspend R/W 0 speed R/W
Bits 6 5
Name uar t_en oe_int_en
Value 0 1 0 1 0 1 0 1 0 1
Settings Inactive UART logic buffers are enabled Inactive Allow to send interruption through USBOEn Inactive (default) Enable A-device to connect if B-device disconnect detected: VP_VM USB mode DAT_SE0 USB mode Inactive (default) Put transceiver in low power mode Set rise and fall times of transmit Low speed Full speed
Default 0 0
4
bdis_acon_en
0
2
dat_se0
0
1
suspend
0
0
speed
0 1
0
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Functional description
STw4811M/STw4811N
SB control register 2
Table 12.
7 vbus_chrg R/W Bits 7
USB control register 2 (address = 06h set and 07h clearh)
6 vbus_ dischrg R/W Name 5 vbus_drv R/W Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4 id_gnd R/W 3 dn_ pulldown R/W 2 dp_ pulldown R/W Settings Inactive Charge VBUS through a resistor Inactive Discharge VBUS through a resistor to ground. Inactive Provide power to VBUS Inactive Connect ID ball to ground Inactive Connect DN pull-down Inactive Connect DP pull-down Inactive Connect DN pull-up Inactive Connect DP pull-up 1 dn_pullup R/W 0 dp_pullup R/W Default 0
vbus_chrg
6
vbus_dischrg
0
5
vbus_drv
0
4
id_gnd
0
3
dn_pulldown
0
2
dp_pulldown
0
1
dn_pullup
0
0
dp_pullup
0
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U
Tw4811M/STw4811N
Functional description
USB interrupt source register
Table 13.
7 cr_int R Bits 7 cr_int
USB Interrupt source register (address = 08h)
6 bdis_acon R Name 5 id_float R Value 0 1 0 1 4 dn_hi R 3 id_gnd_ forced R Settings Inactive DP ball is above the carkit interrupt threshold Inactive Set when bdis_acon_en is set, and transceiver asserts dp_pullup after detecting B-device disconnect. Inactive ID ball floating Inactive DN ball is high Inactive ID ball grounded Inactive DP asserted during SRP, Session valid comparator threshold < 2V 2 V < Session valid comparator threshold A-device VBUS valid comparator threshold < 4.4V A-device VBUS valid comparator threshold > 4.4V 2 dp_hi R 1 sess_vld R 0 vbus_vld R Default 0
6
bdis_acon
0
5
id_float
0 1 0 1 0 1 0 1 0 1 0 1
0
4
dn_hi
0
3
id_gnd_forced
0
2
dp_hi
0
1
sess_vld
0
0
vbus_vld
0
USB interrupt source register indicates the current state of the signals that can generate an interrupt.
USB latch register
Table 14.
Register Bit name Default Type
USB interrupt latch registers (address = 0Ah set and 0Bh clearh)
7 cr_int 0 R/W 6 bdis_ acon 0 R/W 5 id_float 0 R/W 4 dn_hi 0 R/W 3 id_gnd_ forced 0 R/W 2 dp_hi 0 R/W 1 sess_ vld 0 R/W 0 vbus_ vld 0 R/W
USB interrupt latch register indicates which source has generated an interrupt.
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Functional description
STw4811M/STw4811N
SB interrupt enable low register
Table 15.
7 cr_int 0 R/W
USB interrupt enable low register (address = 0Ch and 0Dh)
6 bdis_acon 0 R/W 5 id_float 0 R/W 4 dn_hi 0 R/W 3 id_gnd_ forced 0 R/W 2 dp_hi 0 R/W 1 sess_vld 0 R/W 0 vbus_ vld 0 R/W
USB interrupt enable low register enables interrupts on transition from high to low.
USB interrupt enable high register
Table 16.
7 cr_int R/W
USB interrupt enable high register (address = 0Eh and 0Fh)
6 bdis_acon R/W 5 id_float R/W 4 dn_hi R/W 3 id_gnd_ forced R/W 2 dp_hi R/W 1 0
sess_vld vbus_vld R/W R/W
USB interrupt enable high register enables interrupts on transition from low to high.
Interrupts
Table 13 indicates the signals that can generate interrupts. Any of the signals given in Table 13 can generate an interrupt when the signal becomes either low or high. After an interrupt, the OTG controller is able to read each signal status as well as the bit that indicates whether or not that signal generated the interrupt.
A bit in the interrupt latch register is set when any of the following occurs:
writing "1" to its set address causes the corresponding bit to be set. the corresponding bit in the interrupt enable high register is set, and the associated signal changes from low to high the corresponding bit in the interrupt enable low register is set, and the associated signal changes from high to low
The interrupt latch register is cleared by writing "1" to its clear address.
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U
Tw4811M/STw4811N
Functional description
USB EN register
Table 17.
7 Not used Bits 1 2
USB EN register (address = 10h)
6 B_sess_ end R Name Value 0 1 0 1 0 Inactive Enable USB PHY Threshold for vbus_valid = 4.4 V Threshold for vbus_valid = 3.87 V Vbus voltage is below B_session_end threshold (0.2 to 0.8 V) Vbus voltage is above B_session_end threshold (0.2 to 0.8 V) 5 4 Not used 3 2 th_ Bdevice R/W Settings 1 usb_en R/W 0 not used Default 0 0
usb_en th_Bdevice
6
B_sess_end
1
0
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Functional description
STw4811M/STw4811N
egisters controlled by main I2C BUS
I2C controlled registers are controlled through the main serial I2C interface, SCL and SDA balls.
Configuration 1 register
Table 18.
7 pdn_vaux R/W
Configuration 1 register (11h)
6 it_warn R(1) 5 monitoring_vio_ vmem_vcore R(1) 4 mmc_ls_ status R/W 3 2 vmmc_sel[2:0] R/W 1 0 pdn_ vmmc R/W
1. These bits are reset (0) after reading
Bits 7
Name pdn_vaux
Value 0 1 0 1 0 1 0 Inactive Enable LDO vaux
Settings
Default 0(1)
6
it_warn monitoring_vio_ vmem_vcore
Below temperature threshold Above temperature threshold Outputs in the good range Outputs lower than expected on vio_vmem or vcore Level shifters ON, if `pdn_vmmc' or `external_vmmc' = 1 Level shifters High Impedance, if `pdn_vmmc' or `external_vmmc' =1 1.8V selection 1.8V selection 2.85V selection 3V selection 1.85 V selection 2.6 V selection 2.7 V selection 3.3 V selection Inactive Enable SD/MMC/SDIO function.
0
5
0
4
mmc_ls_status
1 000 001 010 011 100 101 110 111 0 1
0
[3:1] vmmc_sel[2:0]
000
0
pdn_vmmc
0
1. In STw4811M, pdn_vaux = 0 is the default. In STw4811N, pdn_vaux = 1 is the default.
In Flash OTP two registers allow to program STw4811 energy management part. These two registers are at addresses 1E and 1F and must be programmed with 1F register first followed by 1E register.
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R
Tw4811M/STw4811N
Functional description
Power control register at address 1Eh
Table 19.
7
Power control register - General information (address = 1Eh)
6 5 4 3 2 1 0 EN R/W Default 0 0 0
reg address 3 bits LSB's R/W Bits [7:5] [4:1] 0 Name reg address 3 bits data din/ dout 4 bits EN 0 1 Value
data din/dout 4 bits R/W Settings See Table 21 "Address" column (LSB's). See Table 21 control register Read enabled Write enabled
Power control register at address 1Fh
Table 20.
15
Power control register - General information (address = 1Fh)
14 13 Not used 12 11 10 9 8
reg address 2 bits MSB's R/W
Bits [9:8]
Name reg address 2 bits MSB's
Value
Settings See Table 21 "Address" column (MSB's).
Default 0
Power control register mapping
Table 21. Power control register mapping
Address 1Fh reg address Not used 15 14 13 12 11 10 2 bits MSB's 9 8 7 3 bits LSB's 6 5 data din/dout 4 bits 4 3 2 1 Comments EN 0 Reser ved Setting See Table 22 to Table 27 Reser ved Address 1Eh
00h to 04h 05h to 0Ah 0Bh to 1E
Caution:
Only the latest value written in register at address 1E/1F can be read.
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Functional description
STw4811M/STw4811N
ower control register at address 05h
Table 22. Power control register at address 05h
Address 1Fh 15 14 13 12 11 10 9 0 Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 = 1.00V = 1.05V = 1.10V = 1.15V = 1.20V = 1.22V = 1.24V = 1.26V (default) = 1.28V = 1.30V = 1.32V = 1.34V = 1.36V = 1.38V = 1.40V = 1.45V 8 0 7 1 6 0 5 1 4 Address 1Eh 3 2 1 0 EN Default
Not used Bits Name
vcore_sel [3:0] Settings
[4:1]
vcore_sel [3:0]
0111
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P
Tw4811M/STw4811N
Functional description
Power control register at address 06h
Table 23. Power control register at address 06h
Address 1Fh 15 14 13 12 11 10 9 0 8 0 7 1 6 1 5 0 4 vpll_sel [0] Settings = 1.05V = 1.2V = 1.3V = 1.8V = 1.5V = 1.8V = 2.5V = 2.8V USB I2C interface controls USB registers Main I2C interface controls USB registers Address 1Eh 3 2 1 usb_ i2c_ctrl 0 EN
Not used
vaux_sel <1:0>
Bits
Name vpll_sel[1:0] on 06h and 07h address
Value 00 01 10 11 00 01 10 11 0 1
Default
4
11
[3:2] vaux_sel[1:0]
00
1
usb_i2c_ctrl
0
Power control register at address 07h
Table 24. Power control register at address 07h
Address 1Fh 15 14 13 12 11 10 9 0 8 0 7 1 6 1 5 1 4 en_vpll Address 1Eh 3 not used 2 en_ vcore 1 vpll_sel [1] 0 EN
Not used
Bits 4
Name en_vpll
Value 0 1 0 1 -
Settings Disabled / VPLL = OFF Enabled / VPLL = ON(1) Disabled / VCORE = OFF Enabled / VCORE = ON(1) See Table 23
Default 1
2 1
en_vcore vpll_sel[1]
1 -
1. No soft start feature at supply enabled after a disabled/enabled sequence
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Functional description
STw4811M/STw4811N
ower control register at address 08h
Table 25. Power control register at address 08h
Address 1Fh 15 14 13 12 11 10 9 0 8 1 7 0 6 0 5 0 4 en_clk squarer Address 1Eh 3 en_ mo nitoring 2 en_ vana 1 not used 0 EN
Not used
Bits
Name
Value 0 1 0 1 0 1
Settings Disabled ([0; vio_vmem] digital signal) Enabled (master clock input not in the range [0; vio_vmem]) Disabled / MONITORING = OFF Enabled / VCORE & VIO_VMEM monitoring = ON Disabled / VANA = OFF Enabled / VANA = ON
Default
4
en_clock_squarer
0
3
en_monitoring
1
2
en_vana
1
Power control register at address 09h
Table 26. Power control register at address 09h
Address 1Fh 15 14 13 12 11 10 9 8 7 6 5 4 vaux_ sleep Address 1Eh 3 not used 2 1 0
Not used
0
1
0
0
1
vio_ vcore_ vmem_ sleep sleep (1)
(1)
EN
1. Must be left at default value if the master clock is used.
Bits
Name
Value
Settings When PWREN is low: VAUX stays in high power mode VAUX goes in sleep mode When PWREN is low: VIO_VMEM stays in high power mode VIO_VMEM goes in sleep mode When PWREN is low: VCORE stays in high power mode VCORE goes in sleep mode
Default
4
vaux_sleep
0 1
1
2
vio_vmem_sleep
0 1
1
1
vcore_sleep
0 1
1
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P
Tw4811M/STw4811N
Functional description
Power control register at address 0Ah
Table 27. Power control register at address 0Ah
Address 1Fh 15 14 13 12 11 10 9 8 7 6 5 4 vaux_ force_ sleep Address 1Eh 3 not used 2 1 0
Not used
0
1
0
1
0
vio_ vcore_ vmem_ force_ force_ sleep sleep
EN
Bits
Name
Value 0
Settings 0: Vaux keeps the state controlled by Vaux_sleep and Pwren 1: VAUX goes in sleep mode (for any PWREN level) 0: VIO_VMEM keeps the state controlled by vio_vmem_sleep and Pwren 1: VIO_VMEM goes in sleep mode (for any PWREN level) 0: VCORE keeps the state controlled by vcore_sleep and Pwren 1: VCORE goes in sleep mode (for any PWREN level)
Default
4
vaux_force_sleep 1 0 vio_vmem_force_ sleep
0
2
1 0
0
1
vcore_force_sleep 1
0
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Functional description
STw4811M/STw4811N
onfiguration 2 register
Table 28.
7 Not used Bits Name
Configuration 2 register at address = 20h
6 5 Not used R/W Value 0 1 0 1 0 1 0 1 0 1 0 1 4 gpo2 R/W 3 gpo1 R/W 2 mask_it_ wake_up R/W Settings Inactive Mask TWARN interruption (it_twarn bit) through VDDOK Internal LDO VMMC is used External VMMC is used Inactive IT_WAKE_UP ball masked GPO1 in High impedance GPO1 at low level GPO2 in High impedance GPO2 at low level Not used 1 external_ vmmc R/W 0 mask_ twarn R/W Default
0
mask_twarn
0
1 2 3 4 5
external_vmmc mask_it_wake _up gpo1 gpo2 not used
0 0 0 0 0
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C
Tw4811M/STw4811N
Functional description
VCORE_sleep register
Table 29.
Register Bit name Type
VCORE_sleep register at address = 21h
7 6 5 4 vcore_ available R 3 2 1 0
vcore_sleep[3:0] R/W
Bits
Name
Value = 1.00V = 1.05V = 1.10V = 1.15V = 1.20V = 1.22V = 1.24V = 1.26V (default) = 1.28V = 1.30V = 1.32V = 1.34V = 1.36V = 1.38V = 1.40V = 1.45V
Settings
Default
[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 vcore_sleep[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 vcore_available
(1)
0111
4
0 1
Inactive Reach the expected value when Vcore decreases or increases
0
1. read operation reset the value after status read operation from APE, functionality is described in Section 4.3.7: Power supply monitoring
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Functional description
STw4811M/STw4811N
.2 .6
IT generation
STw4811 has three interrupt balls: IT_WAKE_UP: with only VBAT supply, no other supply available, when a USB cable is plugged this interrupt is activated to wake up the host or the modem, depends of application (open drain, active low). By default this feature is available independently of PON level, it can be masked when PON = 1 by `mask_it_wake_up' bit of Configuration 2 register (see Table 28) USBINTn: This interrupt ball is dedicated to USB protocol and sent to multimedia processor. Independently of PWREN ball state, this ball goes to low level if an USB interrupt source is detected. In sleep mode, PWREN = 0, an interrupt source is detected only if unmasked before PWREN goes to low level. VDDOK: This ball has two functions: - When high, it indicates that VIO_VMEM and VCORE output voltages are within the right range and that the device internal temperature is below the maximum allowed temperature. - When low, it indicates that output regulators (VCORE or VIO_VMEM) are not regulated properly or PWREN = "0", or that the temperature is above the allowed threshold (see Thermal shut-down section), `it_warm' bit of Configuration 1 register is the temperature interruption source (see Table 18).
4.2.7
Clock switching and control
This block generates the clock used by the DC/DC converter (USB charge pump, step-down VIO_VMEM and step-down VCORE). STw4811 is able to sustain the master clock frequencies of 26 MHz, 19.2MHz and 13 MHz. If the clock is not detected the internal oscillator is automatically selected. STw4811 allows customers to use the internal clock issued from the internal oscillator to switch the SMPS and charge pump; or, they can provide an external clock and connect it to the master clock input. If it is not necessary, it is recommended to run the device on the internal clock. Nevertheless, if the external clock is used, this clock has some constraints: the master-clk must be provided each time the device is in high power mode. When the device changes from sleep mode to high power mode the master-clk must be active before the device is in high power mode (the master-clk must be available and stable when PWREN pin goes to high level). the only way to stop the use of the master_clk, in HPM mode, is to restart the device with the OFF/ON sequence on PON (PON = 1 then 0 then 1)
Note:
When present the Master clock should remain connected up to sleep mode.
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Tw4811M/STw4811N Figure 9. Clock switching between master and internal clock (1)
internal clock transition external clock
Functional description
* Phase delay is less than 90 between int and ext clock
PON INT_OSC INT_OSC_OK MASTER_CLK_OK Third rising edge after switching PDN_INT_OSC CONTROL_SWITCH
MASTER_DIV_CLK STEP_DOWN_CLK
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Functional description
STw4811M/STw4811N
.3
Power management module
STw4811 includes several regulators that supply the multimedia processor and its peripherals. All regulators can work in different modes depending on the processor needs. When the STw4811 is in `low current mode'", the output current is reduced to save energy via the lower quiescent current. The nominal mode is called high power mode (HPM). The mode is selected by PWREN ball signal according to both multimedia processor and STw4811 state. When PWREN = "0", sleep mode is selected. HPM is selected as default when PWREN = "1". Except for VIO_VMEM, each supply can be powered down by a bit `pdn_(regulator name) or `en_(regulator name)' (Table 18, 24 and 27). In this mode, the regulator is switched off and only a leakage current is present (max. 1A). VCORE, VAUX and VPLL output voltages are programmable, through main I2C interface, using the `(regulator"_sel[x:0])' bits of the power control registers (Table 22 to Table 27). In addition, an output current limitation prevents high current delivery in case of output short circuit. All multimedia processor power supplies have the same soft start to prevent leakage in the multimedia processor device during the start-up phase. There is an exception with VAUX which can be started independently.
4.3.1
Bandgap, biasing and references
Figure 10. Block diagram of biasing and references of the device
BG Voltage reference control All internal references All internal biasing Bias generator VREF_18
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Tw4811M/STw4811N
Functional description
4.3.2
VCORE regulator: DC/DC STEP- DOWN regulator
This regulator drives the core of the multimedia processor. VCORE is a DC/DC step-down regulator that generates the regulated power supply with very high efficiency. The 16 voltage levels enable dynamic voltage and frequency scaling suitable for any supply voltage of CMOS process, they also follow the processor process roadmap. The regulated output voltage level is adjustable via the main I2C interface (SDA, SCL): in high power mode by the power control registers (Table 22), in sleep mode by Vcore_sleep register (Table 29). The master clock (13, 19.2 or 26 MHz) is automatically detected, squared and divided to generate the switching clock of the SMPS. When this clock is not available, regulators run with the internal RC oscillator. The DC/DC step-down regulator has the following main features;
Programmable output voltage, When changing the output voltage value (during a voltage scaling phase) the voltage step must be less than 100mV. In high power mode, 16 levels from 1.0 V to 1.45 V through `vcore_sel [3:0]' bits of power control register (Table 22) In sleep mode,16 levels from 1.0 V to 1.45 V through `vcore_sleep [3:0]' bits of Vcore_sleep register (Table 29).
Note:
By default `vcore_sel' = `vcore_sleep' 3 power domains: `High power mode' when multimedia processor is in run mode, 700 mA full load `Low current mode' when multimedia processor is in sleep mode, 5 mA current capability. Fast switching from low current to high power mode. The regulator is in `low current mode' when multimedia processor is in sleep mode. PWREN signal indicates that the multimedia processor is about to switch to high power mode. VDDOK signal indicates to the multimedia processor that all supplies are in the specified range. The definition of sleep mode is given in section 4.2.3: Sleep mode. `Power down mode' or `standby mode' when regulator is switched off, no consumption (`en_vcore' bit of power control register - Table 24) Soft start circuitry at start up, from power off to high power mode, when PON ball changes from "0" to "1".
Note:
4.3.3
VIO_VMEM regulator: DC/DC step- down regulator
VIO_VMEM step-down regulator has the same structure than VCORE. The VIO_VMEM regulator supplies the IOs of the multimedia processor and its peripherals. This regulator can be used to supply the memories working with the multimedia processor, such as DDR-SDRAM. A switched mode power supply - voltage down converter is used to generate the 1.8 V regulated power supply with very high efficiency. The master clock (13, 19.2 or 26 MHz) is automatically detected and divided to generate the SMPS switching clock. Master clock is squared when bit en_clock_squarer is enabled (Table 25: Power control register at address 08h). When this clock is not available, regulators can run with the internal RC oscillator.
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Functional description ain features
STw4811M/STw4811N
Fixed 1.8 V output voltage Two power domains: `High power mode' when multimedia processor is in run mode - 600 mA full load `Low current mode' when multimedia processor is in sleep mode, 5 mA current capability. Fast switching from low current to high power mode. The regulator is in `low current mode' when multimedia processor is in sleep mode. PWREN signal indicates that the multimedia processor is about to switch to run mode. VDDOK signal indicates to the multimedia processor that all supplies are in the specified range.
Note:
The definition of sleep mode is given in 4.2.3: Sleep mode section. Soft start circuitry at start up, from power off to high power mode, when PON ball changes from "0" to "1".
4.3.4
VPLL
This LDO is dedicated to the multimedia processor PLL (1.05, 1.2, 1.3, 1.8 V) power supply with 10 mA max full load (power control registers - Table 23 and Table 24). Main features
Programmable output voltage, `vpll_sel[1:0]' bits of power control register - Table 23 and Table 24) Two power domains: `High power mode' 10 mA full load `Power down mode' or `standby mode' when regulators are switched off and there is no power consumption (`en_vpll' bit of power control register - Table 24)
Soft start circuitry at start up, from power off to high power mode, when PON ball changes from "0" to "1".
4.3.5
VANA
This LDO is dedicated to the multimedia processor analog function (2.5 V) power supply with 10 mA full load. Main features:
2.5 V output voltage, Two power domains `High power mode' 10 mA full load `Power down mode' or `standby mode' when regulators are switched off and there is no power consumption (`en_vana' bit of power control register - Table 25),
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M
Tw4811M/STw4811N
Functional description
4.3.6
VAUX
This LDO is dedicated either to the multimedia processor input/output signals or to the auxiliar y devices. Power supply values are 1.5, 1.8, 2.5, 2.8 V with 150 mA full load and 0.5 mA in sleep mode. In case of 1.5 V on the output, this LDO can be supplied by using VIO_VMEM DC/DC converter (1.8 V). One pad feed-back is used. Main features:
Programmable output voltage, 4 levels (`vaux_sel[1:0]' bits of power control register - Table 23) Three power domains: `High power mode' when multimedia processor is in run mode, 150 mA full load `Low current mode' when multimedia processor is in sleep mode, 0.5 mA current capability. Fast switching from low current to high power mode.
Note:
The definition of sleep mode is given in 4.2.3: Sleep mode section. `Power down mode' or `standby mode' when regulator is switched off, no power consumption (`pdn_vaux' bit of configuration 1 register - Table 18).
4.3.7
Power supply monitoring
This block monitors the VCORE and VIO_VMEM output voltage. If VCORE or VIO_VMEM drop below the threshold, the multimedia processor is reset, through PORn output ball. In high power mode, this feature can be disabled by setting `en_monitoring' bit of power control register to "0" (Table 25). When VCORE programmed value changes, `vcore_available' bit (Table 29) gives the status of VCORE output supply value and informs the APE that the expected output voltage is reached, this bit is a read only bit and is reset after an APE read operation.
Figure 11 describes `vcore_available' bit behavior.
Figure 11. `vcore_available' bit behavior
Vcore
vcore_available bit read operation to reset bit
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Functional description
STw4811M/STw4811N
.3.8
Power supply domains
Table 30 lists the register bits that control STw4811 supply domains for each supply.
Table 30.
Supply name
Power supply domains
Supply domains Description High power STEP-DOWN Sleep vcore_sleep[3:0] vcore_sleep vcore_force_sleep vio_vmem_sleep vio_vmem_force_sleep vaux_sleep vaux_force_sleep Power down en_vcore
VCORE
vcore_sel[3:0] vpll_sel[1:0] vaux_sel[1:0] vmmc_sel[2:0]
VIO_VMEM STEP-DOWN VPLL VANA VAUX VMMC LDO LDO LDO LDO
en_vpll en_vana pdn_vaux pdn_vmmc
Note:
More details on VMMC supply are given in Section 4.5
4.3.9
Thermal shut-down
A thermal sensor is used to monitor the die temperature.
As soon as the die temperature exceeds the thermal warning rising threshold, VDDOK ball goes to "0" and `it_warn' bit is set to "1" (configuration 1 register - Table 18). The IC turns back VDDOK ball to "1" and `it_warn' bit to "0" when the device temperature drops below the thermal warning falling threshold of the thermal sensor. A second thermal detection level, thermal shutdown threshold, puts all STw4811 supplies OFF, the supplies goes back to ON state when the temperature is under the thermal shutdown threshold and after a new startup phase. Thermal threshold values
Description Min Typ Max Unit
Table 31.
Thermal warning threshold Rising threshold Falling threshold Thermal shutdown threshold Threshold 149 155 164 C 134 117 140 123 149 131 C C
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Tw4811M/STw4811N
Functional description
Figure 12. Thermal threshold temperatures for `it_warn' bit and VDDOK ball
`it_warn' bit All supplies are turn "OFF"
VDDOK ball
Rising warning threshold Shutdown threshold Temperature
4.4
USB OTG module
This transceiver complies with the USB specification;
Universal serial bus specification Rev 2.0 On the go supplement to the USB specification Rev 1.0-a Car kit interface specification (see: OTG transceiver specification Rev 0.92) Full and low speed transceiver (12 Mbit/s and 1.5 Mbit/s data rate) Suppor t data line and VBUS pulsing session request Contains Host Negotiation Protocol (HNP) command and status register Charge pump regulator (5 V at 100 mA) to supply VBUS line of the USB cable VBUS pull-up and pull-down resistors as defined by Session Request Protocol (SRP) VBUS threshold comparators VUSB LDO internal regulator which provides power supply for the bus driver and receiver. ID line detector and interrupt generator Dedicated I²C serial control interface
The USB OTG Transceiver has two modes: USB mode and UART mode. It includes:
Note:
The transceiver complies with USB specification if Vbat is greater than 3.2 V.
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Functional description
STw4811M/STw4811N
.4 .1
Block diagram
Figure 13. USB OTG transceiver block diagram
VBAT_USB CP CN
VBAT_DIG VMINUS_DIG
USB_INTn
vbus_vld sess_vld dn_hi Interrupt dp_hi Control bdis_acon Register id_gnd_forced id_float cr_int usb_en usb_i2c_ctrl B_ sess_end vbus_drv bdis_acon_en dn_pullup dp_pullup Control dn_pulldown Registers dp_pulldown id_gnd vbus_chrg vbus_dischrg speed uar t_en dat_se0 oe_int_en suspend
CL K RE F
VBUS_MONITOR 4.4 V vbus_vld sess_vld B_ sess_end
1.9 V 0.6 V
R_VBU S_SRP
R_VBUS_PD
Charge pump 5V - 100mA
vbus_drv
100 mA VBUS
RA_BUS_IN
vbus_chrg
Gnd vbus_dischrg VUSB_LDO
VBAT_USB
VUSB DP_MONITOR cr_int
DP R 5.7 R
USBSCL USBSDA SCL SDA SW_RESETn
DP < [0.4 to 0.6] V
RXD RXD
TRANCEIVER
dn_pullup dp_pullup
RP U_DP
Diff Tx USBVM USBOEn
S E O_ V M OE _TP _ I N T
RPU_DN
USBVP
DAT_VP
out_diff_Rx Diff Rx suspend
RP D_DN
DP DN SE_DP
RP D_DP
USBRCV
RCV
SINGLE ENDED DECODER
VP
dn_pulldown SE_DN
VM
dp_pulldown
VBAT_USB R RID_PU 0.85*ID 4.7 R id_gnd 0.15*ID R id_gnd id_float
IT_WAKE_UP
Plug detect Management Open Drain OR
ID
sess_vld
ID Detector
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Tw4811M/STw4811N
Functional description
Interrupt management
IT_WAKE_UP: with only VBAT supply, no other supply available, when a USB cable is plugged this interrupt is activated to wake up the host or the modem, depends of application (open drain, active low). By default this feature is available independently of PON level, it can be masked when PON = 1 by `mask_it_wake_up' bit of configuration 2 register (see Table 28) USBINTn: This interrupt ball is dedicated to USB protocol and sent to multimedia processor. Independently of PWREN ball state, this ball goes to low level if an USB interrupt source is detected. In sleep mode, PWREN = 0, an interrupt source is detected only if unmasked before PWREN goes to low level.
VBUS monitoring
These comparators monitor the VBUS voltage. They detect the current status of the VBUS line:
VBUS > 4.4 V means A-Device VBUS_Valid 0.8 V < VBUS < 2 V means A-Device Session Valid and 0.8 V < VBUS < 4 V means BDevice Session Valid. To be compatible with both Session Valid threshold, STw4811 threshold is equal to 1.9 V. VBUS < 0.8 V means B_Device Session End
These three bits generate an interrupt when active (see USB interrupt registers (Table 13)). VUSB LDO: Internal regulator which provides power supply for the bus driver and receiver. ID detector: This block detects the status of the ID line. It is capable of detecting three different states of line:
ball is floating `id_float' bit is high, Threshold detection is equal to 0.85 * Vbattery. ball is tied to ground `id_gnd_forced' bit is high, Threshold detection is equal to 0.15 * Vbattery. ball is grounded via resistor, voltage is between 0.85 * Vbattery and 0.15 * Vbattery. `id_float' and `id_gnd_forced' bits are low.
This detection generates interrupts (see USB interrupt registers (Table 13)). Transceiver: The driver can operate in different modes. It can act as a classical low-speed and full-speed differential driver, as two independent single-ended drivers or as a singleended driver in UART mode. This block contains one differential receiver for the USB mode of operation and two single-ended receivers for USB signaling and UART mode. DP monitor: This block is used to detect car kit peripheral, `cr_int',0.6 V on DP (see USB interrupt registers (Table 13)). Pull up and pull down resistors: Configurable integrated pull-up and pull-down resistor of data line and VBUS (see USB control register 2 (Table 12)).
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Functional description
STw4811M/STw4811N
.4.2
Modes and operations
Power modes
The transceiver power modes are:
active mode suspend mode power down mode
In suspend mode the differential transmitter and receiver are turned off to save power but the USB interface is still active (pull-up and pull-down on, VBUS on). In power down mode, only the serial interface is active and the transceiver is able to detect SRP. In power down mode, ID ball can be grounded by `id_gnd' bit of USB control register 2 (Table 12).
USB modes
The two transceiver modes are:
DAT_SEO mode (dat_se0 = 1 in USB control register 1 - Table 11) VP_VM mode (dat_se0 = 0 in USB control register 1 - Table 11)
Data transmission The transceiver transmits USB data in the following conditions for USB control register 1 (Table 32, Table 33): uar t_en=0; oe_int_en=0 and USBOEn ball at low level. Table 32. Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 0
Inputs USBVP 0 1 x 0 1 0 1 USBVM 0 0 1 0 0 1 1 DP 0 1 0 0 1 0 1 Outputs Comments DN 1 0 0 0 0 1 1 USBRCV Not used Not used Not used DIFF_RX DIFF_RX DIFF_RX DIFF_RX DAT_VP drives the level of DP SE0_VM drives the level of DN Single ended data (zero sent) Single ended data (1 sent) Force single ended zero
USB mode (DAT_SE0) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode)
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Tw4811M/STw4811N Table 33.
Functional description
Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 1
Inputs Outputs Comments USBVP USBVM 0 0 1 0 0 1 1 DP 0 1 0 0 1 0 1 DN 1 0 0 0 0 1 1 USBRCV Not used Not used Not used 0 (off) 0 (off) Driver are suspended 0 (off) 0 (off) Single ended data (zero sent) Single ended data (1 sent) Force single ended zero 0 1 x 0 1 0 1
USB mode (dat_se0) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode)
If oe_int_en = 1 and suspend=1 (USB control register 1 - Table 11), the USBOEn ball becomes an output used to generate an IT to multimedia processor. Data reception The transceiver receives USB data in the following conditions: uar t_en = 0 (USB control register 1); oe_int_en = 1 and USBOEn at high level. Table 34. Data receiver via USB control register 1
Inputs USB mode (dat_se0) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode) 0 (VP_VM mode) Suspend DP 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DN 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 USBVP Diff rcv 1 1 0 Diff rcv 1 0 1 0 1 0 1 0 1 0 1 0 1 USBVM 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 1 USBRCV Not used Not used Not used Not used Not used Not used Not used Not used diff rcv 1 1 0 diff rcv 1 Not used Not used Not used Not used Outputs
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Functional description
STw4811M/STw4811N
ART mode
UART mode is entered by setting the `uart_en' bit to 1 (USB control register 1 - Table 11). The transceiver contains two digital logic level translators between the following balls:
TXD signal: from USBVM ball to DN ball RXD signal: from DP ball to USBVP ball
When not in UART mode the level translators are disabled.
VBUS monitoring and control
The monitoring is made of three comparators that determine if the VBUS voltage is at a valid level for operation:
VBUS VALID: It corresponds to the minimum level on VBUS. Any voltage on VBUS below the threshold is considered to be a fault. During power-up, it is expected that this comparator output is ignored. VBUS SESSION VALID: This threshold is necessary for session request protocol to detect the VBUS pulsing. VBUS SESSION END: Session is ended. In this USB block, a B-device Session End threshold is defined within the range [0.2; 0.8] V. The reason for a low 0.2 V limit is that the leakage current could charge the VBUS up to 0.2 V (maximum).
When the A-device (default master) is power supplied and does not supply VBUS, it presents an input impedance RA_BUS_IN on VBUS of no more than 100 k If the A-device . responds to the VBUS pulsing method of SRP, then the input impedance RA_BUS_IN may not be lower than 40 k . When the A-device supplies power, the rise time TA_VBUS_RISE on VBUS to go from 0 to 4.4 V is less than 100 ms when driving 100 mA and with an external load capacitance of 10 F (in addition to VBUS decoupling capacitance). If VBUS does not reach this voltage within TA_VBUS_RISE maximum time, it indicates that the B-device is drawing more current that the A-device is capable of providing and an over-current condition exists. In this case, the A-device turns VBUS off and terminates the session.
VBUS capacitance
A dual-role device must have a VBUS capacitance CDRD_VBUS value comprised between 1 F and 6.5 F (see charge pump specification). The limit on the decoupling capacitance allows a B-device to differentiate between a powered-down dual-role device and a powereddown standard host. The capacitance on a host is higher than 96 F.
Data line pull-down resistance
The two bits of USB control register, dp_pulldown and dn_pulldown (Table 12) are used to connect/disconnect the pull-down resistors. When an A-device is idle or acting as host, it activates the pull-down resistors RPD on both DP and DN lines. When an A-device is acting as peripheral, it disables RPD on DP, not DN. The A-device can disable both pull-down resistors during the interval of a packet transmission when acting as either host or peripheral. When the line is not used, the pull-down is activated and the maximum level on this ball should not exceed 0.342 V.
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U
Tw4811M/STw4811N
Functional description
Data line pull-up resistance
The two bits of USB control register dp_pullup and dn_pullup (Table 12) are used to connect/disconnect pull-up resistors. Full-speed and low-speed devices are differentiated by the position of the pull-up resistor from the peripheral device. A pull-up resistor is connected to DP line for a full-speed device and a pull-up resistor is connected to DN line for a low-speed device. The pull-up resistor value is in the range of 900 to 1600 when the bus is idle and 1425 to 3100 when the upstream device is transmitting.
Session Request Protocol (SRP)
To save power, the OTG supplement allows an A-device to leave the VBUS turned off when the bus is not being used. If the B-device wants to use the bus when VBUS is turned off, then it requires the A-device to supply power on VBUS using the Session Request Protocol (SRP).
Initial conditions
The B-device does not attempt to start a new session until it has determined if the A-device has detected the end of the previous session. The B-device must ensure that VBUS is below VBUS_SESSION_END before requesting a new session. Additionally, the B-device switches a pull-down resistor (R_VBUS_PD) from VBUS to ground in order to quicken the discharge process as long as the B-device does not draw more than 8 mA from VBUS. R_VBUS_PD is activated by bit `vbus_dischrg' of USB control register 2, (Table 12). When the B-device detects that VBUS is below the VBUS_SESSION_END and that both DP and DN have been low (SEO) for at least 2 ms, then any previous session on the Adevice is over and a new session can start.
Data-line pulsing
To indicate a request for a new session using the data line pulsing, the B-device turns on the DP pull-up resistor for 5 ms to 10 ms (only at full speed, no DN pulsing). The DP pull-up resistor is connected to VUSB (regulator output voltage). Timing is controlled by the USB digital control.
VBUS pulsing
To indicate a request for a new session using the VBUS pulsing method, the B-device waits for the initial conditions and then drives VBUS. VBUS is driven for a long enough period for a capacitance on VBUS that is smaller than 2x6.5 F to be charged to 2.1 V while a capacitance on VBUS higher than 97 F is not charged above 2.0 V. In this USB block, the VBUS_SESSION_VALID threshold is used to determine if an A-device is DRD (dual role device) or a standard host. The B-device VBUS pulsing block is designed so that the maximum drawn current does not exceed 8 mA. In this USB block, the pull-up is 600 +/- 30%. If a B-device is attached to a standard device, the pull-up must be disconnected after the defined timing to prevent damage of standard hosts not designed to withstand a voltage externally applied to VBUS.
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Functional description Session Request Protocol (SRP)
STw4811M/STw4811N
If the B-device is in correct condition to start a new session, it first performs data line pulsing, followed by VBUS pulsing. When VBUS next crosses the SESSION VALID threshold, the B- device considers a session to be in progress and asserts the DP or DN data line within 100 ms. After SRP initialization, the B- device is set up to wait for at least 5 seconds for the A-device to respond before informing the user that the consumption attempt has failed.
Host Negotiation Protocol (HNP)
At the start of a session, the A-device has the role of host as default. During a session, the host role can be transferred back and forth between the A-device and the B-device any number of times using the Host Negotiation Protocol (HNP). The sequence of events for this exchange of host role is described in the "On the Go Supplement to the USB 2.0 Specification" (rev 1.0) as follow: The A-device puts the bus in the suspend state The B-device simulates a disconnect by de-asserting its DP pull-up The A-device detects SE0 on the bus and asserts its DP pull-up The B-device detects that DP line is high and takes the role of the host.
ID detector
In either active or suspended power mode, the ID detector detects the condition of the ID line and differentiates between the following three conditions:
ID ball floating: (e.g. with USB B-device connected) ID ball shorted to ground: (e.g. with USB A-device connected) ID ball connected to ground through resistor RACC_ID: (e.g.with an accessory).
The transceiver pulls the ID ball to VID_HI (VBAT) through a resistance of RID_PU when an accessory is plugged in. In this case, the ID ball is externally connected to ground via Racc_ID resistor. Two comparators are used to detect the ID voltage: VID_GND and VID_FLOAT (Figure 13). The ID detector also has a switch that can be used to ground the ID ball. This switch is controlled by `id_gnd bit' of USB control register 2 (Table 12); This pull-down is used for CEA_KARKIT purposes.
Car kit interrupt detector
The transceiver is able to detect when the DP line is below the car kit interrupt threshold `cr_int', (see USB interrupt register in Table 13 and refer to OTG specifications, Rev 0.92, §2.7, p13).
Charge pump
From VBAT_USB, the charge pump supplies VBUS, `vbus_drv' bit of USB control register 2 (Table 12) is used to enable/disable the charge pump. If VBUS is "ON" before going to sleep mode, it remains "ON" in sleep mode.
LDO USB
From VBAT_USB, a LDO provides VUSB supply, `usb_en' bit of USB_EN register (Table 17) is used to enable/disable the VUSB LDO and the transceiver.
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Tw4811M/STw4811N
Functional description
4.4.3
USB enable control
STw4811 OFF
In this state: PON ball = 0 In this state, the overall system is able to detect USB connection through IT_WAKE_UP ball and with VBUS session valid comparator and ID detection ON. IT_WAKE_UP ball is activated (low level if tied by an external Pull Up resistor to VIO or VBAT) in either of the two following cases:
When a mini A connector cable is connected and ID goes low When activity on VBUS, that is a mini B is connected and is able to communicate. This mode is used to wake-up the platform. In this configuration, USBINTn ball is not enabled and IT_WAKE_UP ball cannot be masked by `mask_it_wake_up' bit (Table 28).
STw4811 ON, USB driver not enabled
In this state: PON = 1 If `mask_it_wake_up' bit is set to "0", IT_WAKE_UP ball has the same behavior as above (PON = 0) and turns ON the transceiver, `usb_en' bit set to "1" (Table 17). If `mask_it_wake_up' is set to "1", IT_WAKE_UP ball feature is disabled and always stay at level "1" if tied by an external pull up resistor to VIO or VBAT and the transceiver is not turn ON. In sleep mode and in HIGH POWER mode, USBINTn ball is now enabled. If the USB cable is already connected while STw4811 is starting, the USB driver will be enabled when power management is ready.
Wake-up USB driver conditions A plug-in on a mini A-device and active ID detector B device is connected and ready to start data transfer, VBUS is driven high (session valid high) Activity on USB registers (00h to 0Fh - Table 9 to Table 16). Multimedia processor ready to wake-up and set-up USB PHY. Possibility to force PHY high (enable) when writing `usb_en' = 1 in USB EN register (Table 17) External it_wake_up =0 usb_en = 1 by writing to I2C USB interface Access to any other USB register (00h to 0Fh) it_wake_up = 1, and only then Set `usb_en' bit of USB EN register (Table 17) to "0"
Set condition: one among the following possibilities
Power down USB driver conditions in order to set the USB driver to power down mode:
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Functional description
STw4811M/STw4811N
.5
SD/MMC/SDIO module
Figure 14. SD/MMC/SDIO block diagram
SD/ MMC/SDIO interface
MCCMDDIR MCDATA0DIR MCDATA2DIR MCDATA31DIR VMMC L DO 150 mA CLKOUT Driver 5*RB VIO_VMEM 3*RA M CCM D MCDATA0 MCDATA[3:1] MCFBCLK
RB 3*RA
RC Rs
VBAT_VMMC
EMIF
MCCLK Level
SD, MMC SDIO OR cards
Dz
shifter CM DOUT DATAOUT0 DATAOUT[3:1] LATCHCLK
Dz
4.5.1
SD/MMC/SDIO LDO supply
The Vmmc LDO is supplied via the input Vbat_Vmmc. According to the protection diode design, the voltage on this input pin Vbat_Vmmc must be always higher or equal to the battery voltage. Vbat_Vmmc >= Vbat By programming `vmmc_sel[2:0] bits of configuration 1 register (Table 18), this LDO provides the power supply (1.8 V, 1.85 V, 2.6 V, 2.7 V, 2.85 V, 3 V, 3.3 V) with a 150 mA current compliance for any of the following peripherals.
SD card MMC card SDIO card
If an application does not request to use the level shifter feature, this LDO can be used to supply an other peripheral, in this case, to reduce the internal current consumption due to level shifter it is recommended to set to "1" `mmc_ls_status' bit of configuration 1 register (Table 18). If an application, like HDD, requests more than 150 mA current supply and the use of the internal level shifters, internal LDO must be disabled. The application will be supplied by an external LDO and internal level shifter will be directly supplied by the external LDO. In this configuration, `pdn_vmmc' bit is set to "0", `mmc_ls_status' is set to "0" (Table 18) and `external_vmmc' bit is set to "1" (Table 28).
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Tw4811M/STw4811N
Functional description
4.5.2
Level shifters
Signal shifting cards voltage level value is automatically done by the multimedia processor system. Following a card detection, the multimedia processor starts the SD/MMC/SDIO application by writing in the configuration 1 register (Table 18) to program LDO VMMC output supply and then starts the protocol initialization. The module includes:
Five bidirectional level shifter channels compatible with 1.8 V, 1.85 V, 2.6 V, 2.7 V, 2.85 V, 3.0 V, 3.3 V Two unidirectional lines for clock: multimedia processor to card and feedback clock to multimedia processor for synchronization. Four control signals for channel direction. When direction balls (MCCMDDIR, MCDATA0DIR, MCDATA2DIR, MCDATA31DIR) are at low level, data is transmitted from Card to APE. When direction balls are at high level data is transmitted from APE to card.
When the level shifters are "ON", the APE interface MCDATA[3:0] and the MCCMD balls have a 1.5 Mohm pull up resistor to VIO_VMEM. It is possible to connect another card on the APE interface (1.8 V interface) for this:
set to "1" `mmc_ls_status' bits of configuration 1 register (Table 18) with this configuration: the APE interface MCDATA[3:0] and the MCCMD balls are put in high impedance and the pull up resistors are disconnected. the card interface DATAOUT[3:0] and the CMDOUT balls are set to "1" with an internal 1.5 Mohm pull up resistor the card clock, CLKOUT ball, is set to "0" and the APE feedback clock, MCFBCLK ball is configured in high impedance.
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Electrical and timing characteristics
STw4811M/STw4811N
Electrical and timing characteristics
Otherwise specified typical parameters are defined for T = 25 C / VBAT = 3.6 V.
5.1
Absolute maximum rating
Table 35.
Symbol
STw4811 absolute maximum ratings
Description Maximum power supply Values -0.5 to 7 -30 to +85 model(1) -2 to +2 -300 to +1000 Units V C kV V
Ta
Maximum operating ambient temperature Human body
VESD
Electrostatic discharge model
Charge device model(2)
1. HBM tests have been performed in compliance with JESD22-A114-B and ESD STM 5.1-2001.HBM 2. CDM tests have been performed in compliance with CDM ANSI-ESD STM 5.3.1-1999
5.2
Package dissipation
Table 36.
Symbol
Package dissipation
Description Min. Typ. Max. Units
TFBGA 84 6x6x1.2mm 0.5mm ball pitch RTHJ-A Thermal resistance junction to ambient 70 C/W
VFBGA84 4.6x4.6x1.0mm 0.4mm ball pitch RTHJ-A Thermal resistance junction to ambient 76 C/W
5.3
Note:
Power supply
STw4811 has different ways to go in sleep mode.
The different possibilities for VCORE, VIO_VMEM and VAUX to be programmed to sleep mode are given in Table 26 and Table 27. Taking in account the bit programming from Table 26 and Table 27, sleep mode is summarized with the following formula: SLEEP = (Vxxx_SLEEP x PWREN) + (Vxxx_FORCE_SLEEP) = 1 (Vxx = VCORE or VIO_VMEM or VAUX)
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Tw4811M/STw4811N
Electrical and timing characteristics
Note:
The configuration Vxxx_SLEEP = 0 (device in active mode) and Vxxx_FORCE_SLEEP = 1 (device in sleep mode, but no priority level on this bit) is forbidden.
In all the following tables: "High power mode" is defined as "SLEEP = `0'" "Sleep mode" is defined as "SLEEP = `1'"
Use Table 27 to refer to each Vxxx supply (VCORE or VIO_VMEM or VAUX).
5.3.1
Operating conditions
Table 37.
Symbol VBAT IQSLEEP Quiescent current IQSTDBY
Operating conditions (temperature range: -30 to +85 C)
Description Power supply Sleep mode VBAT = 3.6 V OFF mode VBAT = 3.6 V Test conditions Min. 2.7 140 4 Typ. Max. 4.8 Units V A A
5.3.2
VREF18
Table 38.
Symbol VBAT VREF_18 PSRR
VREF18
Description Supply voltage Output voltage Power supply rejection ratio Noise Vpp = 0.3 V f 100 kHz 100 Hz f 100 kHz Test conditions Min. 2.7 1.78 1.8 60 30 7.77 9.46 Typ. Max. 4.8 1.84 Units V V dB V ms
tS
Settling time
S
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Electrical and timing characteristics
STw4811M/STw4811N
.3 .3
VCORE DC/DC step-down converter
Table 39.
Symbol
VCORE DC/DC step-down converter
Description Test conditions Min. Typ. Max. Units
VCORE regulator in high power mode (SLEEP = 0) unless otherwise specified, VCORE = 1.26V VBAT VRIPPLE Input power supply Battery voltage Output voltage ripple 'vcore_sel'[3:0] 1111 1110 1101 1100 1011 1010 1001 1000 0111 (default) 0110 0101 0100 0011 0010 0001 0000 -3.7% 2.7 3.6 6 4.8 V mVpp
VOUT
Programmable output voltage
-4.25%
-5%
1.45 1.40 1.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 1.15 1.10 1.05 1.00
+3.7%
V
+4.25%
+5% 700 mA % 10 10 mV mV A A A dB
IOUT PEFF LIR LDR(1) ISHORT IQ ILKG PSRR(1) LIRT LDRT
Output current Power efficiency Line regulation Load regulation Shor t circuit current limitation Quiescent current Power-down current Power supply rejection Transient line regulation Transient load regulation IOUT = 0 mA `en_vcore' = 0 Vpp = 0.3 V [0; 20] kHz VBAT = 300 mV tR = tF = 10 s IOUT = [1; 700] mA tR = tF = 100 ns 40 7 70 VBAT = 3.6 V IOUT = 200 mA VBAT: [2.7; 4.8]V IOUT: [0.1; 700] mA 0.9 1 .2 130 86
1.4 200 1
mV mV
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Tw4811M/STw4811N Table 39.
Symbol
Electrical and timing characteristics VCORE DC/DC step-down converter (continued)
Description Test conditions Min. Typ. Max. Units
VCORE regulator in sleep mode (SLEEP= `1') VBAT VRIPPLE LIR LDR IOUT PEFF IQ LIRT Input power supply Battery voltage VCORE output voltage ripple Line regulation Load regulation VCORE output current Power efficiency Quiescent current Transient line regulation VBAT= 3.6 V IOUT: [0.1; 5] mA IOUT = 0 mA VBAT= 300 mV tR = tF = 10 s 85 20 7 30 VBAT: [2.7; 4.8]V IOUT: [0.1; 5] mA 2.7 3.6 6 10 10 5 4.8 V mVpp mV mV mA % A mV
1. Guaranteed by design
5.3.4
VIO_VMEM DC/DC step-down converter
Table 40.
Symbol
VIO_VMEM DC/DC step-down converter
Description Test conditions Min. Typ. Max. Units
VIO_VMEM regulator in high power mode (SLEEP = `0') VBAT VOUT VRIPPLE LIR LDR(2) IOUT PEFF Input power supply Battery voltage Output voltage Output ripple Line regulation Load regulation Output current Power efficiency Shor t circuit current limitation Quiescent current Power supply rejection Transient line regulation Transient load regulation IOUT = 0 mA Vpp = 0.3 V [0; 20] kHz VBAT = 300 mV tR = tF = 10 s IOUT= [1; 600] mA tR = tF = 100 ns 40 7 70 VBAT = 3.6 V, VIO = 1.8 V IOUT= 200 mA 0.9 VBAT: [2.7; 4.8]V IOUT: [0.1; 600] mA
(1)
2.7 -3%
3.6 1.8 6
4.8 +3%
V V mVpp
10 10 600
mV mV mA
90 1.2 130 1.4 250
% A A dB mV mV
ISHORT IQ PSRR(2) LIRT LDRT
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Electrical and timing characteristics Table 40.
Symbol
STw4811M/STw4811N
VIO_VMEM DC/DC step-down converter (continued)
Description Test conditions Min. Typ. Max. Units
IO_VMEM regulator in sleep mode (SLEEP='1') VBAT VRIPPLE LIR LDR IOUT PEFF IQ LIRT Input power supply Battery voltage Output ripple Line regulation Load regulation Output current Power efficiency Quiescent current Transient line regulation VBAT = 3.6 V IOUT = [0.1; 5] mA IOUT = 0 mA VBAT = 300 mV tR = tF = 10 s 2 85 20 VBAT: [2.7; 4.8]V IOUT: [0.1; 5] mA 2.7 3.6 10 10 10 5 4.8 V mVpp mV mV mA % A mV
1. Including output voltage temperature coefficient, DC line and load regulations, voltage reference accuracy, industrial manufacturing tolerances and ripple voltage due to switching 2. Guaranteed by design
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V
Tw4811M/STw4811N
Electrical and timing characteristics
5.3.5
LDO regulators
VPLL
Table 41.
Symbol
LDO regulators - VPLL
Description Test conditions Min. Typ. Max. Units
VPLL regulator in high power mode unless otherwise specified, VPLL = 1.8 V VBAT Input power supply Battery voltage 'vpll_sel'[1:0] 11 (default) 10 01 00 2.7 3.6 1.8 1.3 1.2 1.05 3.5 95 IOUT = 0 mA EN_VPLL = 0 Vpp = 0.3 V f < 10 kHz 10 kHz < f <100 kHz VBAT: [2.7; 4.8]V IOUT: [0.1; 10] mA VBAT = 300 mV tR = tF = 10 s IOUT = [0.1; 10] mA tR = tF = 1 s at 1 kHz BW = 100 Hz 1 1 250 130 30 4.8 V
VOUT
Output voltage
-3%
+3%
V
IOUT ISHORT IQ ILKG
Output current Shor t-circuit limitation Quiescent current Power-down current Power supply rejection Line regulation Load regulation Transient line regulation Transient load regulation Noise density
10 165 40 1
mA mA A A
PSRR(1)
55 45 5 10
dB dB mV mV mV mV nVrms Hz
LIR LDR LIRT LDRT En(1)
------------
1. Guaranteed by design
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Electrical and timing characteristics
STw4811M/STw4811N
ANA
Table 42.
Symbol
LDO regulators - VANA
Description Test conditions Min. Typ. Max. Units
VANA regulator in high power mode VBAT VOUT IOUT ISHORT IQ ILKG PSRR(1) LIR LDR LIRT LDRT Input power supply Battery voltage Output voltage Output current Shor t-circuit limitation Quiescent current Power-down current Power supply rejection Line regulation Load regulation Transient line regulation Transient load regulation IOUT = 0 mA EN_VANA = 0 Vpp = 0.3 V f < 10 kHz VBAT: [2.7; 4.8] V IOUT: [0.1; 10] mA VBAT = 300 mV tR = tF = 10 s IOUT = [0.1; 10] mA tR = tF = 1 s 2 15 45 5 5 39 51 2.7 -5% 3.6 2.5 4.8 +5% 10 64 30 1 V V mA mA A A dB mV mV mV mV
1. Guaranteed by design
VAUX
Table 43.
Symbol
LDO regulators - VAUX
Description Test conditions Min. Typ. Max. Units
VAUX regulator in high power mode (pdn_vaux = 1, SLEEP = 0) VOUT = 1.5V VBAT Input power supply VOUT = 1.8/2.5 V VOUT = 2.8 V 'vaux_sel'[1:0] 00 (default) 01 10 11 1.7 2.7 3 -3% 3 .6 3.6 1 .5 1.8 2.5 2.8 4.8 4.8 4.8 +3% V V V
VOUT
Output voltage
IOUT ISHORT IQ
Output current Shor t-circuit limitation Quiescent current IOUT = 0 mA 220
150 410 30
mA mA A
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V
Tw4811M/STw4811N Table 43.
Symbol ILKG PSRR(1)
Electrical and timing characteristics LDO regulators - VAUX (continued)
Description Power-down current Power supply rejection Line regulation Load regulation Transient line regulation Transient load regulation Settling time Test conditions 'pdn_vaux' = 0 VOUT=1.5 V Vpp = 0.3 V f < 10 kHz VOUT=1.5 V VBAT: [2.7; 4.8]V VOUT=1.5 V IOUT= [0.1; 150] mA VBAT = 300 mV tR = tF = 10 s IOUT = [10; 90%] mA tR = tF = 1 s 2 Min. Typ. Max. 1 Units A
40
dB
LIR LDR(1) LIRT
5 10
mV mV mV
LDRT tS
35 100
mV s
VAUX regulator in sleep mode ('pdn_vaux'= 1, SLEEP='1') VOUT = 1.5V VIO_VMEM supply VBAT Input power supply VOUT = 1.8/2.5 V VOUT = 2.8 V IOUT IQ PSRR(1) Output current Quiescent current Power supply rejection Line regulation Load regulation Transient line regulation Transient load regulation IOUT = 0 mA VOUT=1.5 V Vpp = 0.3 V f < 10 kHz VOUT=1.5 V VBAT: [2.7; 4.8]V VOUT=1.5 V IOUT= [10; 90%] A VBAT = 300 mV tR = tF = 10 s IOUT = [10; 90%] A tR = tF = 1 s 2 35 38 1.7 2.7 3 3 .6 3.6 4.8 4.8 4.8 500 20 A A dB V V
LIR LDR LIRT LDRT
5 10
mV mV mV mV
1. Guaranteed by design
S
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Electrical and timing characteristics
STw4811M/STw4811N
.3.6
Power supply monitoring
This block monitors the VCORE and VIO_VMEM output voltage. If VCORE or VIO_VMEM drops below the threshold, the multimedia processor is reset. Table 44.
Symbol Threshold THCORE(1) Threshold VCORE THVIO(1) Threshold VIO_VMEM -3% -3% VCORE-150 1.65 +3% +3% mV V
Power supply monitoring
Description Test conditions Min. Typ. Max. Units
Comparators VBAT tRES HYFALL HYRIS Supply voltage Response time Hysteresis (input voltage falling) Hysteresis (input voltage rising) 2.7 3.6 100 26 +4 4.8 V ns mV mV
1. Guaranteed by design
5.4
5.4.1
Digital specifications
CMOS input/output static characteristics: I2C interface
Table 45.
Symbol I²C interface(1) VIL VIH II L II H Low level input voltage High level input voltage Low level input current High level input current Low level output voltage High level output voltage IOL = 3mA (with open drain or open collector) IOL = 3mA (with open drain or open collector) 0.8*VIO 0.7*VIO -1.0 -1.0 1.0 1.0 0.3*VIO V V A A
CMOS input/output static characteristics: I²C interface
Description Test conditions Min. Typ. Max. Units
VOL
0.2*VIO
V
VOH
V
1. Vio is for VIO_VMEM
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Tw4811M/STw4811N
Electrical and timing characteristics
5.4.2
CMOS input/output dynamic characteristics: I2C interface
Table 46.
Symbol I²C interface (Figure 8) Fscl thigh tlow tr tf thd_sta tsu_sta thd_dat tsu_dat tsu_sto tbuf Cb Clock frequency Clock pulse width high Clock pulse width low 600 1300
(1)
CMOS input/output dynamic characteristics: I²C interface
Description Min. Typ. Max. Units
400
kHz ns ns
SDA, SCL, USBSDA, USBSCL rise time 20+0.1*Cb SDA, SCL, USBSDA, USBSCL fall time Star t condition hold time Star t condition set up time Data input hold time Data input set up time Stop condition set up time Bus free time Capacitive load for each bus line
300 300
ns ns ns ns ns ns ns ns
20+0.1*Cb 600 600 0 100 600 1300
400
pF
1. Cb = total capacitance of one bus line in pF
S
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Electrical and timing characteristics
STw4811M/STw4811N
.4.3
CMOS input/output static characteristics: VIO level
USB and control I/Os
Table 47.
Symbol
VIO level: USB and control I/Os
Description Test conditions Min. Typ. Max. Units
SW_RESETn, VDDOK, PORN, PWREN, TCXO_EN, REQUEST_MC, CLK32K, CLK32K_IN, USBOEN, USBVP, USBVM, USBRCV, USBINTn, MASTER_CLK VIL(1) VIH II L II H CIN VOL VOH tO F tO R CI/O Low level input voltage High level input voltage Low level input current High level input current Input capacitance Low level output voltage High level output voltage Output fall time Output rise time Driving capability IOL = 4 mA IOL = 4 mA Capacitance 10pF Capacitance 10pF 0.8*Vio 10 10 100 0.7*Vio -1.0 -1.0 1.5 1.5 10 0.2*Vio 0.3*Vio V V A A pF V V ns ns pF
1. Vio for VIO_VMEM
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Tw4811M/STw4811N
Electrical and timing characteristics
MMC interface
Table 48.
Symbol
VIO level: MMC interface
Description Test conditions Min. Typ. Max. Units
MMC interface: MCCLK, MCFBCLK, MCCMDDIR, MCCMD, MCDATA2DIR, MCDAT2, MCDATA0DIR, MCDAT0, MCDAT31DIR, MCDAT3, MCDAT1 VIL(1) VIH II L II H CIN VOL VOH CI/O Low level input voltage High level input voltage Low level input current High level input current Input capacitance Low level output voltage High level output voltage Driving capability at 52 MHz IOL = 15 mA IOL = 15 mA 0.8*Vio 30 0.7*Vio -1.0 -1.0 1.5 1.5 10 0.2*Vio 0.3*Vio V V A A pF V V pF
1. Vio for VIO_VMEM
S
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Electrical and timing characteristics
STw4811M/STw4811N
.4.4
CMOS input/output static characteristics: VBAT level
Table 49.
Symbol
CMOS input/output static characteristics: VBAT level
Description Test conditions Min. Typ. Max. Units
IT_WAKE_UP, PON, GPO1, GPO2 VIL VIH II L II H CIN VOL Low level input voltage High level input voltage Low level input current High level input current Input capacitance Low level output voltage High level output voltage Output fall time Output rise time Driving capability IT_WAKE_UP, GPO1, GPO2 IOL = 2 mA IT_WAKE_UP, GPO1, GPO2 IOL = 2 mA Capacitance 10pF Capacitance 10pF 0.8*Vbat 5 50 100 PON PON PON PON 0.7*Vbat -1 . 0 -1 . 0 1.5 1.5 10 0.2*Vbat 0.3*Vbat V V A A pF V
VOH tO F tO R CI/O
V ns ns pF
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Tw4811M/STw4811N
Electrical and timing characteristics
5.4.5
CMOS input/output static characteristics: VMMC level
Table 50.
Symbol
CMOS input/output static characteristics VMMC level
Description Test conditions Min. Typ. Max. Units
DATAOUT0, DATAOUT1, DATAOUT2, DATAOUT3, CMDOUT, LATCHCLK, CLKOUT VIL VIH II L II H CIN VOL VOH CI/O Low level input voltage High level input voltage Low level input current High level input current Input capacitance Low level output voltage High level output voltage Driving capability IOL = 25 mA IOL = 25 mA 0.8*VMMC 40 pF 0.7*VMMC -1.0 -1.0 1.5 1.5 10 0.2*VMMC A A pF 0.3*VMMC
S
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Electrical and timing characteristics
STw4811M/STw4811N
.5
USB OTG transceiver
Table 51.
Symbol UART mode tR Rise time CLOAD= [50;100] pF [10; 90] % of VOH-VOL CLOAD= [50;100] pF 10. . ..90% of VOH-VOL CLOAD= [50;100] pF 50% of |VOH-VOL| CLOAD= [50;100] pF 50% of |VOH-VOL| 100 ns
USB OTG transceiver
Description Test conditions Min. Typ. Max. Units
tF
Fall time Drive propagation delay low => high Drive propagation delay high => low
100
ns
tPLH tPHL
100 100
ns ns
USB full speed mode (DP & DN signals) tR tF DRFM OSCV PDEL Rise time Fall time Differential rise an fall time matching Output signal crossover voltage Propagation delay
USBVP & USBVM : - Trise & Tfall < 1 ns - Skew < 0.66 ns
4 4 90 1.3
20 20 111 2 18
ns ns % V ns
USB low speed mode (DP & DN signals) tR tF DRFM OSCV Rise time Fall time Differential rise an fall time matching Output signal crossover voltage 75 75 80 1.3 300 300 125 2 ns ns % V
VBUS comparators VBAT tRR tF R Input power supply Rising reacting time Fall reacting time Battery voltage 3.1 3.6 1.7 2.1 4 .8 V s s
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Tw4811M/STw4811N Table 51.
Symbol
Electrical and timing characteristics USB OTG transceiver (continued)
Description Test conditions Min. Typ. Max. Units
Threshold VBUS monitoring VAval Vth_dev VBses VBsess_end VBUS RA_BUS_
IN
VBUS valid Threshold device VBUS session valid B_session_end `th_Bdevice' = 1
4.4 3.77 1.8 0.2
4.5 3.87
4 .6 3.97 2 0.8
V V V V
40 VBUS = [0; 4.4] V ILOAD = 100mA External cap 10F
100
k
TA_VBUS_
RISE
100
ms
Data line pull-down resistance RPD_DPDN Data line pull-up resistance RPU_DP RPU_DN PULL-DOWN on VBUS RVBUS_PD PULL-UP on VBUS RVBUS_SRP ID VID_GND VID_HI (VBAT) VID_FLOAT RPU_ID RPD_ID Carkit threshold detection cR_INT Carkit interrupt threshold 0.4 0 .6 V ID_GND comparator 2.7 V < VBAT < 4.8 threshold V Batter y level ID_FLOAT comparator threshold 70 2.7 0.15* VBAT 3.6 0.85* VBAT 100 130 10 4 .8 V V 420 600 780 650 925 1200 Bus idle Bus driven Bus idle Bus driven 900 1425 900 1425 1200 2300 1200 2300 1600 3100 1600 3100 14 19 25 k
V k k
S
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Electrical and timing characteristics Table 51.
Symbol ransceiver VOH_TXD_
DAT
STw4811M/STw4811N
USB OTG transceiver (continued)
Description Test conditions Min. Typ. Max. Units
TXD output high on DN TXD output low on DN RXD input high on DP RXD input low on DP
ISOURCE = 500 A ISINK = 2mA
2.4
3.6 0 .4
V V V
VOL_TXD_
DAT
VIH_RXD
_DAT
2 0.8
VIL_RXD_
DAT
V
Charge pump VBAT VBUS Input power supply Output voltage Battery voltage Current load up to 100 mA [0;4.8] V) Ext. load: 100 mA + External cap = 10F No Load Current load 8 mA Current load 100mA VUSB+0.1 4.75 3.6 5 4.8 5.25 V V
tS
Settling time
1.2
ms
IQ VRipple IOUT
Quiescent current Amplitude output ripple on VBUS Output current
2.7 25 40 100
mA mV mV mA % %
Eff
Efficiency
VBAT = 3.0V IOUT =100mA VBAT= 3.6V. IOUT = 8 mA.
85 60
VUSB regulator VBAT(1) Input voltage Battery voltage: VBAT min = VOUT + 0.1V VBAT min= VOUT + 0.1V VUSB+0.1 3.6 5.5 V
VOUT ISHORT IQ PSRR(2) LIRT
Output voltage Shor t circuit current limitation Quiescent current Power supply rejection Transient line regulation
3.0
3.1
3.2 320
V mA A dB
No load VBAT= VOUT+0.2V f < 20 kHz VBAT = 300 mV tR = tF = 10s. 45 5
70
mV
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T
Tw4811M/STw4811N Table 51.
Symbol tS tD
Electrical and timing characteristics USB OTG transceiver (continued)
Description Settling time OFF->ON Discharge time ON>OFF Test conditions IOUT = 0mA IOUT = 0mA Min. Typ. 25 400 Max. Units s s
1. From 4.8 V to 5.5 V, charge pump is "Off" and no OTG feature is provided 2. Guaranteed by design
5.6
SD/MMC/SDIO card interface
Table 52.
Symbol
SD/MMC/SDIO card interface
Description Test conditions Min. Typ. Max. Units
VMMC regulator specifications ('pdn_vmmc' = 1) VOUT = 3.3 V VOUT = 3 V VOUT = 2.85 V VOUT = 2.7 V VOUT = 2.6 V VOUT = 1.8/1.85 V 3.55 3.25 3.1 2.95 2.85 2.7
VIN
Input voltage
3.6
5.5
V
VOUT
Output voltage
-3 %
3.3 3 2.85 2.7 2.6 1.85 1.8
+3%
V
IOUT ISHORT IQ ILKG PSRR(1)
Output current Shor t circuit current limitation Quiescent current Power-down current Power supply rejection Line regulation Load regulation Transient line regulation IOUT = 0 mA 'pdn_vmmc' = 0 IOUT = 150 mA Vpp = 0.3 V f < 20 kHz VOUT=2.85 V VBAT: [3.1; 4.8]V VOUT=2.85 V IOUT= [1; 150] mA VOUT=2.85 V VBAT: 3.1 to 3.4V tR = tF = 10 s. 2 240 360
150 600 30 1
mA mA A A
45
dB
LIR(1) LDR(1)
5 10
mV mV
LIRT
mV
S
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Electrical and timing characteristics Table 52.
Symbol
STw4811M/STw4811N
SD/MMC/SDIO card interface (continued)
Description Test conditions Min. Typ. Max. Units
VMMC regulator specifications ('pdn_vmmc' = 1)
DRT
Transient load regulation Settling time OFF->ON Discharge time ON>OFF
IOUT = [1; 150] mA tR = tF = 1 s IOUT = 0 mA IOUT = 0 mA
25 100 1
mV s ms
tS tD
Bus line specifications RA(2) RB Pull-up resistor Pull-down resistor Clock frequency data transfert mode To prevent bus from floating To prevent bus from floating With CL = 30pF 1.5 1.5 M M
fDT
52
MHz
fI D TPHC TPCH
Clock frequency With CL = 30pF identification mode Propagation time from Host to card Propagation time from card to host Clock /data skew time from host to card Clock /data skew time from card to host Rise time Fall time Between host and STw4811 Bus line capacitance f < 52 MHz
400 7 7
kHz ns ns
Figure 15 Figure 15 Figure 15 Reference is CLKOUT Figure 15 Reference is MMCLK
TSHC
+/- 0.5
ns
TSCH TR TF C1LINE
+/- 0.5 3 3 20(3)
ns ns ns pF
C2LINE
Bus line Between STw4811 capacitance and MMC card f < 52 MHz
20 + 20(4)
pF
1. Guaranteed by design 2. MMC interface pull up resistors are in EMIF06-HCM01F2 device (7 K for CMD; 75 K for Data wires) 3. 20 pF for equivalent board parasitic capacitance. 4. 20 pF for EMIF06 protection + 20 pF for board parasitic capacitance.
74/85
L
Tw4811M/STw4811N Figure 15. Propagation and clock/data skew times
2 ns
MCCLK MCCMD MCDATA[3:0] MCFBCLK CLKOUT CMDOUT DATAOUT[3:0] LATCHCLK 90% 10% 90% 50% 10% 2 ns
Electrical and timing characteristics
2 ns
90% 50%
TSHC
TPHC
t
MCCLK 10%
CLKOUT
50% MCDATA[3:0] DATAOUT[3:0]
TPHC 2 ns
CLKOUT CMDOUT DATAOUT[3:0] LATCHCLK MCCLK MCCMD MCDATA[3:0] MCFBCLK 90% 10% 90% 50% 10% 2 ns
t
2 ns
90% 50%
TSCH
TPCH
t
CLKOUT 10%
MCCLK
50% DATAOUT[3:0] MCDATA[3:0]
TPCH
t
S
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Application information
STw4811M/STw4811N
Application information
6.1 Components list
Table 53.
Name C1 22F C4 C2 C3 C5 C6 C7 C8 C10 C13 C9 C11 C12 C13, C14, C15, C16, C17 L1 4.7H L2 See Table 54 for recommended coils Coil VCORE DC/DC 470nF 4.7F 2.2F 1 F 1F 10F In the complete system application, the sum of the capacitors connected on each STw4811 ball must never be less than 30% of the value indicated in the typical value column of this table. This includes all capacitor parameters: production dispersion DC bias voltage applied temperature range of the complete system application aging VCORE output filter VBAT_VIOVMEM decoupling VBAT_ANA decoupling VBAT_VCORE decoupling VPLL output filter VANA output filter VREF output filter VUSB output filter VAUX output filter Flying capacitor for charge pump VBUS output filter (tank charge pump capacitor) VSD_MMC output filter Vbattery input voltage decoupling capacitors Coil VIOVMEM DC/DC
Components list
Typical value Comments Function VIO_VMEM output filter
Table 54.
Supplier
Recommended coils
Part number VLF3010AT-4R7MR70 DCR () 0.28 0.16 0.14 0.15 0.32 0.19 Irms(1) (A) 0.7 0.74 1.1 1.1 1.1 1.1 L x l x h (mm * mm * mm) 2.8 * 2.6 * 1.0 2.8 * 2.6 * 1.2 3.7 * 3.5 * 1.2 5.5 * 4.2 * 1.8 3.3 * 3.3 * 1.4 3.2 * 2.5 * 2.0
TDK
VLF3012AT-4R7MR74 VLF4012AT-4R7M1R1 DO1605T-472MX
Coilcraft
DO3314-472ML ME3320-472MX
1. Irms: 30% decrease of initial value
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Tw4811M/STw4811N Table 55. Other ST components
Name EMIF02 EMIF06 O |
