SABRE-LL-I
Combo motor driver
Preliminary Data
Features
Configurable device 4 full bridges to generate Up 2 DC motor drivers and 1 stepper motor driver or 4 DC motor drivers
Bridges (1 & 2) additional configurations are Super DC 2 half bridges 1 super half bridge 2 switches 1 super switch Bridges (3 & 4) additional configurations are: Same as bridges 1&2, listed above 2 buck regulators (bridge 3) 1 super buck regulator Batter y charger (bridge 4) One variable voltage buck switching regulator One switching regulator controller One linear regulator Bidirectional serial interface Programmable watchdog function Integrated power sequencing and supervisory functions with fault signaling through serial interface and external reset pin Thermal shutdown protection with thermal warning capability Very low power dissipation in shut-down mode (~35 mW) Device summary
Part number SABRE-LL-I
TQFP64 exposed pad
Aux features Operational amplifiers Comparators Pass switches Multi-channels 9 bit ADC GPIOs
Description
S.A.B.ReTM (structured architecture of bridges and regulators) is a new concept of IC in the motion & power supply field. ST aim is to follow the S.A.B.Re specification and to offer to the customer an IC with a wide number of features, that can be configured and customized: motor drivers, regulators, high precision A/D converter, operational amplifiers and voltage comparators. The start up configuration can be defined by the GPIOs and then through the serial interface; a customization can be done through a metal layer in order to set more complex functions.
Table 1.
Package TQFP64
Packing Tray
November 2007
Rev 1
1/141
www.st.com 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
S ABRE -LL-I
Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 3
S.A.B.Re's main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Global specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 3.2 Absolute maximum rating specifications . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating ratings specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
Internal supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 4.2 4.3 4.4 4.5 4.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VSupplyInt regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VSupplyInt specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Charge pump regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 V3v3 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 V3v3 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
Supervisory system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 5.2 5.3 5.4 5.5 5.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power on reset (POR) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 nRESET generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 nRESET specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Thermal shut down generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 TSD specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
Watchdog circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1 6.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Watchdog specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7
Internal clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1 7.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Internal clock specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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8
Start-up configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1 8.2 8.3 8.4 8.5 8.6 8.7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Basic device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Slave device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Master device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Single device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Sub-configurations for slave, master or single device modes . . . . . . . . . 29
8.7.1 8.7.2 8.7.3 8.7.4 8.7.5 8.7.6 Bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Primar y regulator mode (KP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Regulators mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Simple regulator mode (KT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bridge+ VEXT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Secondary regulators mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9
Power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.1 10.2 10.3 10.4 10.5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 nAWAKE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11
Linear main regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12
Main switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
12.1 12.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Pulse skipping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
13
Switching regulator controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.1 13.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Pulse skipping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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13.3 13.4 13.5
Output equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Switching regulator controller specifications . . . . . . . . . . . . . . . . . . . . . . 45 Switching regulator controller application considerations . . . . . . . . . . . . . 45
14
Power bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
14.1 14.2 14.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Power bridges operating specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Possible configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
14.3.1 14.3.2 14.3.3 14.3.4 14.3.5 14.3.6 14.3.7 Full bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Parallel configuration (super bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Half bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Switch configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Bipolar stepper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Synchronous buck regulator configuration . . . . . . . . . . . . . . . . . . . . . . . 64 Regulation loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
15
AD converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
15.1 15.2 15.3 15.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 A2D specification with A2dType=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 A2D specification with A2dType=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Voltage divider specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
16
Current DAC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
16.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
17
Operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
17.1 17.2 17.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Operational amplifiers specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Operational amplifiers used as comparators specifications . . . . . . . . . . . 85
18
Low voltage power switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
18.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
19
General purpose PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
19.1 19.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 General purpose PWM generators 1 and 2 (AuxPwm1 and AuxPwm2) . 88
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19.3
Programmable PWM generator (GpPwm) . . . . . . . . . . . . . . . . . . . . . . . . 88
20
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
20.1 20.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Interrupt controller monitored signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
21
Digital comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
21.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
22
GPIO pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.9 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 GPIO[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 GPIO[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 GPIO[2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 GPIO[3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 GPIO[4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 GPIO[5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 GPIO[6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 GPIO[7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
22.10 GPIO[8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 22.11 GPIO[9] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 22.12 GPIO[10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 22.13 GPIO[11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 22.14 GPIO[12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 22.15 GPIO[13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 22.16 GPIO[14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
23
Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
23.1 23.2 Read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
24 25
Registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Schematic samples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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26
Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
26.1 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
27 28
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
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List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 IC operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VSupplyInt specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VPump specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VSupplyInt specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power on reset specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Stretch time selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 nRESET circuit specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 TSD circuit specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Watchdog timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Watchdog specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Internal clock specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Possible start-up pins state symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Start-up correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 nAWAKE function specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 System linear regulator operating specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Switching regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Main switching regulator PWM specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Main switching regulator current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Main switching regulator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Switching regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Switching regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Switching regulator controller operating specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Switching regulator controller operating specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Switching regulator controller application feedback reference . . . . . . . . . . . . . . . . . . . . . . 46 PWM selection truth for bridge 1 or 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 PWM selection truth for bridge 3 or 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Power bridges operating specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Bridge selection truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Bridge 3 and 4 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Full bridge truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Half bridge truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Switch truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Stepper specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Sequencer drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Stepper mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Stepper sequencer direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Internal sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Blanking times specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Stepper off time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Stepper fast decay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Switching regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Pwm specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Operating specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Battery charger control loop FBRef specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Battery charger control loop CurrRef specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100.
S ABRE -LL-I
Battery charger regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Battery charger operating specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 ADC truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Channel addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ADC sample times when working as a 8-bit ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ADC sample time when working as a 9-bit ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ADC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 ADC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Voltage divider specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Current DAC truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Current DAC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Configurable 3.3V operational amplifier specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Configurable 3.3V operational amplifier used as comparator specification . . . . . . . . . . . . 85 3.3V low power switch specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Interrupt controller event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Interrupt controller specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Comparison type truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 DataX selection truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 GPIO functions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 GPIO[0] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 GPIO[0] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 GPIO[1] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 GPIO[1] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 GPIO[2] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 GPIO[2] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 GPIO[3] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 GPIO[3] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 GPIO[4] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 GPIO[4] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 GPIO[5] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 GPIO[5] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 GPIO[6] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 GPIO[6] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 GPIO[7] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 GPIO[7] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 GPIO[8] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 GPIO[8] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 GPIO[9] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 GPIO[9] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 GPIO[10] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 GPIO[10] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 GPIO[11] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 GPIO[11] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 GPIO[12] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 GPIO[12] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 GPIO[13] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 GPIO[13] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 GPIO[14] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 GPIO[14] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SPI interface specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
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List of tables
Table 101. Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Table 102. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
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List of figures
S ABRE -LL-I
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VSupplyInt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 nReset generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Watchdog circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Standby mode function description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 nAWAKE function block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Linear main regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Linear main regulator external bipolar example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Main switching regulator functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Switching regulator controller functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Switching regulator controller output driving equivalent circuit . . . . . . . . . . . . . . . . . . . . . . 44 H Bridge block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Bridge 1 and 2 PWM selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Super bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Half bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Bipolar stepper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Regulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Internal comparator functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Battery charger control loop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Li-ion battery charge profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Simple buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 A2D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Current DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Configurable 3.3V operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Low power switch block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Low power switch block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Digital Comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 GPIO[0] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 GPIO[1] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 GPIO[2] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 GPIO[3] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 GPIO[4] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 GPIO[5] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 GPIO[6] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 GPIO[7] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 GPIO[8] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 GPIO[9] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 GPIO[10] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 GPIO[11] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 GPIO[12] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 GPIO[13] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 GPIO[14] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SPI read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SPI write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SPI input timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 SPI output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Application with 2 DC motors, 1 stepper motor and 3 power supplies . . . . . . . . . . . . . . . 134 Application with 2 DC motors, a battery charger and 5 power supplies . . . . . . . . . . . . . . 135
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List of figures TQFP64 mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
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General description
S ABRE -LL-I
1
1.1
General description
Overview
S.A.B.Re represents a new concept of IC in motion & power supply field. The aim that ST followed in defining S.A.B.Re specification was to offer to the customer an IC with a wide number of features: motor drivers, regulators, high precision A/D converter, operational amplifiers, voltage comparators and many other circuits can easily be configured and customized. The device configuration can be defined by programming the IC via the Serial Interface while a deeper customization can be done through metal layer in order to set more complex functions.
Figure 1.
Block diagram
OP.Amps
(2x) 3.3V Pass Switch
Digital auxiliary
Digital compar.
Current DAC
SPI
SA B R e
Thermal Manager Analog Mux
S/H
Power sequencing
Osc.
Start Up config.
Bridge 1
GPIOs
Bridge 3
Rsense
Supervisory & Reset Manager
Main Switching regulator
Switching Reg. controller
Charge Pump
Int. Ref. Volt
Main Linear regulator
Internal regulators
Batt. Charg. circuitry
Stepper circuitry
Bridge 2
ADC
Bridge 4
Rsense
Note:
See following "S.A.B.Re's Main features" for a detailed description of possible configurations.
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SABRE-LL-I
S.A.B.Re's main features
2
S.A.B.Re's main features
S.A.B.Re includes the following circuits:
Four widely configurable full bridges: Bridges 1 and 2: Diagonal RDSon: 0.6 typ. Max operative current = 2.5A. Diagonal RDSon: 0.85 typ. Max operative current = 1.5A.
Bridges 3 and 4:
Possible configurations for each bridge are the following: Bridge 1: DC motor driver. Super DC (bridge 1 and 2 paralleled form superbridge1). 2 independent half bridges. 1 super half bridge (bridge 1 side A and bridge 1 side B paralleled form superhalfbridge1). 2 independent switches (high or low side). 1 super switch (high or low side).
Bridge 2 has the same configurations of bridge 1. Bridge 3 has the same configurations of bridge 1 (bridge 3 and 4 paralleled form superbridge2) plus the following: ½ Stepper motor driver. 2 buck regulators (VAUX1_SW, VAUX2_SW). 1 Super buck regulator (VAUX1//2_SW). ½ stepper motor driver. 1 super buck regulator (VAUX3_SW). Batter y charger.
Bridge 4 has the same configurations of bridge 1 plus the following:
One buck type switching regulator (VMAIN_SW) with: Output regulated voltage range: 1-5 Volts. Output load current: 3.0 A. Internal output power DMOS. Internal soft start sequence. Internal PWM generation. Switching frequency: ~250kHz. Pulse skipping strategy control. Output regulated voltage range: 1-30 Volts. Selectable current limitation. Internal PWM generation. Pulse skipping strategy control.
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One switching regulator controller (VEXT_SW) with:
S.A.B.Re's main features
S ABRE -LL-I
One linear regulator (VMAIN_LIN) that can be used to generate low current/low ripple voltages. This regulator can be used to drive an external bipolar pass transistor to generate high current/low ripple output voltages. One bidirectional serial interface with address detection so that different ICs can share the same data bus. Integrated power sequencing and supervisory functions with fault signaling through serial interface and external reset pin. Four teen general purpose I/Os that can be used to drive/read internal/external analog/logic signals. One 8-bit/9-bit A/D converter (100KS/sec @ 9-bit, 200KS/sec @8-bit). It can be used to measure most of the internal signals, of the input pins and a voltage proportional to IC temperature. Current sink DAC: Three output current ranges: up to 0.64/6.4/64 mA. 64 (6-bit programmable) available current levels for each range. 5V output tolerant. 3.3V supply, rail to rail input compatibility, internally compensated. They can have all pins externally accessible or can be internally configured as a buffer o make internal reference voltages available outside of the chip. Unity gain bandwidth > 1MHz. They can also be set as comparators with 3.3V input compatibility and low offset.
Two operational amplifiers:
Two 3.3V pass switches with 1 RDSon and short circuit protected. Programmable watchdog function. Thermal shutdown protection with thermal warning capability. Very low power dissipation in "Low Power mode" (~35mW) S.A.B.Re is intended to maximize the use of its components, so when an internal circuit is not used it could be employed for other applications. Bridge 3, for example, can be used as a full bridge or to implement two switching regulators with synchronous rectification: to obtain this flexibility S.A.B.Re includes 2 separate regulation loops for these regulators; when the bridge is used as a motor driver, the 2 regulation loops can be redirected on general purpose I/Os to leave the possibility to assembly a switching regulator by only adding an external FET.
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Global specifications
3
3.1
Global specifications
Absolute maximum rating specifications
The following specifications define the maximum range of voltages or currents for S.A.B.Re. Stresses above these absolute maximum specifications may cause permanent damage to the device. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table 2. Absolute maximum rating
Description VSupply voltage VGPIO_SPI voltage 3.3V pins input voltage Switching regulators output pin voltage range Switching regulators min pulsed voltage Charge pump pins voltage Junction temperature(2) For less than 500ns
(1)
Parameter VSupply_Abs VGPIO_SPI_Abs V3V3pin_Abs VSw_Abs VSw_pulse VPump_Abs Tj_Abs
Test condition
Min
Max 40 3.9 3.9
Unit V V V V V
-1 -3
VSupply
15 -40 0 190 TSD
V C C
Storage Operating
1. This value is useful to define the voltage rating for external capacitor to be connected from VPump to VSupply. VPump is internally generated and can never be supplied by external voltage source nor is intended to provide voltage to external loads. 2. TSD is the thermal shut down temperature of the device.
3.2
Operating ratings specifications
Table 3. IC operating ratings
Description VSupply voltage range VSupply operative current VSupply shut down state current VGPIO_SPI voltage range VGPIO_SPI operative current 3.3V input pins voltage range Junction temperature Operating
(2) (1)
Parameter VSupply_Op ISupply_Op IShut_down VGPIO_SPI_OP IVGPIO_SPI_OP V3v3pin_Op Tj_Abs
Test condition
Min 23
Max 38 15 1.5
Unit V mA mA V mA V C
2.4
3.6 TBD
-0.3 0
3.6 125.
1. Operating Supply current is measured with System regulators operating but not loaded. 2. Operating VGPIO_SPI current is measured with all circuits supplied by VGPIO_SPI (GPIO's, operational amplifiers and pass switches) enabled but not loaded.
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Internal supplies
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4
4.1
Internal supplies
Overview
S.A.B.Re includes three internal regulators used to provide a regulated voltage to internal circuits. The internal regulators are the following: - VSupplyInt regulator. - Charge pump regulator. - V3v3 regulator.
4.2
VSupplyInt regulator
VSupplyInt is the output of an internal regulator used to supply some internal circuits. This regulator is not intended to provide external current so it must not be used to supply external loads. An external capacitor must always be connected to this pin (preferably towards VSupply pin). Figure 2. VSupplyInt pin
Vsupply VsupplyInt
IS_Int_TYP
SABRe internal circuits SABRe GND
The VSupplyInt pin may also be externally connected to VSupply pin by means of an external resistor REXT: this allows REXT, particularly when VSupply is at the max values of the operative supply range, to dissipate power that otherwise would be dissipated inside the chip. The choice of the optimal resistor depends on the application since it is strictly depending on both VSupply and the current used inside the chip (that is changing with the chosen configuration).
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Internal supplies
4.3
VSupplyInt specifications
Table 4. VSupplyInt specification
Description VSupplyInt output voltage VSupplyInt operative current External resistor value External capacitor Test condition
(1) (2)
Parameter VS_Int_RNG IS_Int_TYP RExt CExt
Min 18
Typ 19.5 11 1000
Max 21
Unit V mA
VSupply=32V IS_Int=12mA(3) 80
1.5 120
nF
100
1. This value is useful to define the voltage rating for external capacitor to be connected from VSupply to VSupplyInt. 2. This typical value is only intended to give an extimation of the current consumption when S.A.B.Re is configured in simple regulators mode (see following Chapter 8.7.4) at the end of the start up sequence and with no load on regulators. This typical value allows a raw choose of the external resistor but the definitive choose must be done according to following Note 3). 3. REXT could be chosen by applying this formula: REXT = (VSupply min - VS_Int max)/(IS_Int max). IS_Int max is depending from the chosen configuration and represents the total current needed by the circuits connected to this pin.
4.4
Charge pump regulator
S.A.B.Re implements a charge pump regulator to generate a voltage over VSupply.This voltage is used to drive internal circuits and the external FET driver and cannot be used for any other purpose. This circuit is always under the supervisory circuit control, so no regulator can start before the VPump voltage reaches its undervoltage rising threshold. If VPump voltage falls down below its under voltage falling threshold, all the regulators will be switched off. The charge pump circuit is disabled when S.A.B.Re is in "Low Power mode". Table 5.
Parameter VPump FPump CFLY CBOOST
VPump specification
Description Regulated Voltage VPump clock frequency Flying capacitor Boost capacitor Test condition VSupply=32V Fosc = 16MHz typ Min VSupply +10.5 Typ VSupply +12.5 Fosc/64 100 1 Max VSupply +14.5 Unit V KHz nF F
4.5
V3v3 regulator
V3v3 is the output of an internal regulator used to supply some low voltage internal circuits. This regulator is not intended to provide external current so it must not be used to supply external loads. An external capacitor must always be connected from this pin to gnd.
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Internal supplies
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4.6
V3v3 specifications
Table 6.
Parameter V3V3 CExt
VSupplyInt specification
Description V3v3 output voltage External capacitor Test condition VSupply=32V Min 3.15 80 Typ 3.3 100 Max 3.45 120 Unit V nF
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Supervisory system
5
5.1
Supervisory system
Overview
The supervisory circuitry monitors the state of several functions inside S.A.B.Re and resets the device (and other ICs if connected to nRESET pin) when the monitored functions are outside their normal range. Supervisory circuitry can be divided into three main blocks: Power on reset (POR) generation circuitry. nRESET (nRST_int) generation circuitry. Thermal shut down (TSD) generation circuitry.
POR circuitry monitors the voltages that S.A.B.Re needs to guarantee its own functionality; nRESET circuitry controls if S.A.B.Re's main voltages are inside their normal range; TSD is the thermal shut down of the chip in case of overheating.
5.2
Power on reset (POR) circuit
Power on reset circuit monitors VSupply, and V3v3 voltages. The purpose of this circuit is to set the device is in a stable and controlled status until the minimum supply voltages that guarantee the device functionality are reached. The output signal of this circuit (in the following indicated as "POR") becomes active when VSupply or V3v3 go under their falling threshold. When POR output signal is active, all functions and all flags inside S.A.B.Re are set in their reset state; once POR signal comes back from off state (meaning monitored voltages are above their rising threshold), the power up sequence is re-initialized Table 7.
.
Power on reset specifications
Description Test condition InRESET = 1mA VSupply falling Min 4 6 3 V3V3 falling V3V3 rising 1.9 2.2 2.7 0.5 1.5 9 Typ Max Unit V V s V V V s
Parameter
VSupply_POR_valid VSupply voltage for POR valid VSupply_POR_fall tSupply_POR_filt V3V3_POR_fall V3V3_POR_rise V3V3_POR_hys t3V3_POR_filt VSupply POR falling threshold VSupply POR filter Time V3v3 POR falling threshold V3v3 POR rising threshold V3v3 POR hysteresis V3v3 PORfilter time
5.3
nRESET generation circuit
The nRESET circuit monitors VSupply, VSupply_int, VPump, VGPIO_SPI and all system regulators (VSystem) voltages. The purpose of this circuit is to prevent the device functionality until the monitored voltages reach their operative value (please note that V3v3
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Supervisory system
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is monitored by POR, so it must be above its minimum value, otherwise nRESET circuit is not active). This circuit generates an internal reset signal (in the following indicated as "nRST_int") that will also be signaled to external circuits by pulling low the nRESET pin. The signal nRST_int becomes active in the following cases: 1. When one of the following voltages is lower than its own under voltage threshold: 2. 3. 4. VSupply and VSupply_int. VPump. VSystem (all switching or linear system regulators voltages). VGPIO_SPI.
When watchdog timer counter (see Chapter 6) elapse the watchdog timeout time (only if watchdog function is enabled). When S.A.B.Re is in "Low Power mode". When EnExtSoftRst bit in SoftResReg register is at logic level = "1" and a "SoftRes" command is applied (see SoftResReg register description in Chapter 25).
When an nRST_int event is caused by above cases, the nRESET pin will stay low for a "stretch" time that starts from the moment that nRST_int signal returns in the operative state. This stretch time can be selected by setting the ID[1:0] bits in the SampleID register according to following table: Table 8. Stretch time selection
Selected stretch time ID[1] 0 0 1 1 ID[0] Typ 0 1 0 1 16ms 32ms 48ms 64ms Default state Note
When nRST_int becomes active (logic level = "0") it sets in their reset state some of the functions inside S.A.B.Re. The main functions that will be reset by nRST_int signal are the following: Serial interface will be reset and will not accept any other command. The bridges 1 and 2 will place their outputs in high impedance and PWM and direction signals will be reset. Not system regulators will be powered off. AD converter will be powered off. GPIOs will be powered off. Current DAC will be powered off. Operational amplifiers will be powered off. Watchdog count will be reset (while Watchdog flags won't be reset). Interrupt controller will be powered off. Digital comparator will be powered off.
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Supervisory system Additionally the system regulators will be powered off but only if the voltage that caused the nRST_int event is checked before the system regulator in the power up sequence. This means that: all system regulators will be powered off if nRST_int is caused by VSupply, VSupply_int, VPump (and also if V3v3 causes a POR); no one of the system regulators will be powered off if nRST_int is caused by VGPIO_SPI; only the system regulators that follows the system regulator that caused the nRST_int in power up sequence will be powered off.
5.4
nRESET specifications
Table 9. nRESET circuit specifications
Description nRESET Low level output voltage nRESET fall time nRESET delay time VSupply falling threshold VSupply rising threshold VSupply hysteresis VSupply UV filter time VSupplyInt falling threshold VSupplyInt rising threshold VSupplyInt hysteresis VSupplyInt UV filter time VPump falling threshold VPump rising threshold VPump hysteresis VPump UV filter time VGPIO_SPI falling threshold VGPIO_SPI rising threshold VGPIO_SPI hysteresis VGPIO_SPI UV filter time 250 3.5 1.8 2.4 1.5 3.5 VSupply +7 VSupply + 9.5 1.5 3.5 14.0 17.5 2 3.5 Test condition I=10mA I=1mA C=50pF(1)
(2)
Parameter nRST_VOL nRST_fall nRST_del VSupply_UV_f VSupply_UV_r VSupply_UV_hys tSupply_UV VS_Int_UV_f VS_Int_UV_r VS_Int_UV_hys tS_Int_UV VPump_UV_f VPump_UV_r VPump_UV_hys tPump_UV VGPIO_SPI_UV_f VGPIO_SPI_UVr VGPIO_SPI_hys tGPIO_SPI_UV
Min
Typ
Max 0.4 15 150
Unit V ns ns V
18.5 23
V V us V V V s V V V us V V mV us
1. Measured between 10% and 90% of output voltage transition. 2. Measured from a fault detection to 50% of output voltage transition.
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Supervisory system Figure 3. nReset generation circuit
nRST_in Filter
S ABRE -LL-I
UV comparator UV Filter
V SupplyUV
V SupplyInt
UV comparator UV Filter
V SupplyIntUV
Low Power Mode
V Supply
V Pump
UV comparator UV Filter
nRESET pin
V PumpUV
nGateCtrl
nRESET pin Driver
V SysX
UV comparator UV Filter SystemregulatorsUV
POR
WD_En_nRst
V SysY
UV comparator UV Filter
to SPI
Note:
All regulator voltages included in power up sequence (VSysX VSysY in Figure 3) will be considered as nRESET circuit voltages.
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WatchDog Elapsed
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Supervisory system
5.5
Thermal shut down generation circuit
The third component of the supervisory circuit is the thermal shut down generation circuit. This circuit generates two different flags depending on the IC temperature: the "TSD" flag indicates that the IC temperature is greater than the maximum allowable temperature. the "Warm" flag, that can be read using serial interface, becomes active at a lower temperature respect to TSD signal, therefore it can be used to prevent the IC from reaching over temperature.
When a TSD event occurs, S.A.B.Re will enter in the reset state placing the bridges in high impedance and turning off all regulators and other circuits until the internal temperature decreases below the Warm temperature. At this point, S.A.B.Re will restart the power up sequence and TSD bit will be set and will be readable as soon as S.A.B.Re will come out from the reset state. This TSD bit can be reset in three ways: by writing a logic level `1' in the ClearTSD bit in the ICTemp register (see Chapter 25); by a POR event; by entering in "Low Power Mode".
The Warm bit, set by S.A.B.Re when IC is working over the warming temperature, can be read using the SPI interface. Once this bit is set it can be reset in three ways: by writing a logic level `1' in the ClearWarm bit; by a POR event; by entering in "Low Power Mode".
The thermal sensor voltage can be converted using the internal A/D: this way the microcontroller can directly measure the IC temperature. To avoid unwanted commutation especially when temperature is near the thresholds, the output signal is filtered for both TSD and Warm.
5.6
TSD specifications
Table 10. TSD circuit specifications
Description Thermal shut down temperature Warming temperature Thermal shut down to warming difference Thermal shut down filter time Warming filter time Test condition Min Typ 170 140 30 8 8 Max Unit C C C us us
Parameter TTSD TWARM TDIFF tTSD_FILT tWARM_FILT
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Watchdog circuit
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6
6.1
Watchdog circuit
Overview
The Watchdog timer can be used to reset S.A.B.Re if it is not serviced by the firmware that can periodically write at logic level "1' the ClrWDog bit in the WatchDogStatus register. This circuit is disabled by default; firmware can enable it by setting at logic level `1' the WDEnable bit in the WatchDogCfg register. When the Watchdog timeout event happens, S.A.B.Re sets to `1' a latched bit WDTimeOut in theWatchDogStatus register that can be read using SPI interface; once this bit is set it can be cleared in three ways: by writing a `1' in the WDClear bit in the WatchDogStatus register. by writing a `1' in the SoftReset bit in the WatchDogStatus register. by a POR event.
The Watchdog function includes also a warning bit WDWarning to indicate, via serial interface or via the circuit called Interrupt Controller (see Chapter 21) that the watchdog is near to its timeout; this bit is asserted to logic level "1" exactly one watch dog clock period (WD_Tclk) before the watchdog timeout happens. Firmware can enable the WDTimeOut signal to cause an "nRst_int" event by setting to logic `1' the WDEnnRst bit. Figure 4. Watchdog circuit block diagram
WDdelay[3:0]
WDEnable
ClrWDog
To nRSTint generation circuit
WD_req_nRst WD_En_nRst
Fosc
Frequency divider
WD_clk Watchdog counter
WDTimeOut WDWarning
To SPI
The watchdog timeout has an imprecision of maximum one WD_Tclk. The effective programmed WD time is changed in the register only when the watchdog circuit is serviced by firmware with ClrWDog bit. At this time the watchdog timer is reset and the new value of the WD delay value is loaded. The watchdog timer can be programmed to generate different timeouts using the WDdelay[3:0] bits in the WatchDogCfg register according to following table:
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SABRE-LL-I Table 11. Watchdog timeout specifications
Watchdog circuit
WD timeout WDdelay[3:0] Typ 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 8*WD_Tclk 9*WD_Tclk 10*WD_Tclk 11*WD_Tclk 12*WD_Tclk 13*WD_Tclk 14*WD_Tclk 15*WD_Tclk 16*WD_Tclk 17*WD_Tclk 18*WD_Tclk 19*WD_Tclk 20*WD_Tclk 21*WD_Tclk 22*WD_Tclk 23*WD_Tclk
6.2
Watchdog specifications
Table 12.
Parameter WD_Tclk
Watchdog specifications
Description Watchdog clock period Test condition Mi n Typ Tosc * 222 Max Unit s
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Internal clock oscillator
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7
7.1
Internal clock oscillator
Overview
S.A.B.Re includes a free running oscillator that does not require any external components. This circuit is used to generate the time base needed to generate the internal timings; the typical frequency is 16MHz. The oscillator circuit starts as soon as the IC exits from the power on reset condition and it is stopped only when in "Low Power mode".
7.2
Internal clock specifications
Table 13.
Parameter
Internal clock specifications
Description Oscillator frequency Oscillator period Test condition Mi n Typ Max Unit
Fosc Tosc
V3V3 =3.3V
14.4
16 1/Fosc
17.6
MHz
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Start-up configurations
8
8.1
Start-up configurations
Overview
S.A.B.Re start-up configuration is selected by setting in different states the GPIO[0], GPIO[3] and GPIO[4] pins. Each of these is a three state input pin and is able to distinguish among the following situations: Table 14. Possible start-up pins state symbol
Pin condition Shor ted to ground Shor ted to V3v3 pin Floating
Note: "Shorted" means: R1KOhm; "Z" means: R10KOhm, C200pF
State symbol 0 1 Z
8.2
Operation modes
When VSupply voltage is applied to S.A.B.Re, the internal regulator V3v3, used to supply the logic circuits inside the device, starts its functionality. When it reaches its final value, S.A.B.Re enables the GPIO[0] pin state read circuitry, and, after a time TpinSample, it will sample the GPIO[0] state. If it is found to be in high impedance, S.A.B.Re does not consider GPIO[3] and GPIO[4] pins state and starts its "Basic device" mode sequence. If GPIO[0] is found to be connected to ground or to V3v3, S.A.B.Re checks the state of GPIO[3] and GPIO[4] pins to select its start-up configuration. The possible configurations can be classified in four "Major" modes: 1. 2. 3. 4. Basic device. Slave device. Master device. Single device.
Hereafter is reported the correspondence table between GPIO[X] state and S.A.B.Re configurations.
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Start-up configurations Table 15. Start-up correspondence
Pin state(1) Major mode GPIO[0] Z 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 GPIO[3] X 0 0 0 Z Z Z 1 1 1 0 0 0 Z Z Z 1 1 1 GPIO[4] X 0 Z 1 Single 0 Z 1 0 Z 1 Master 0 Z 1 0 Z 1 Slave 0 Z 1 Simple regulator Bridge + VEXT Simple regulator Bridge + VEXT Simple regulator Bridge + VEXT Basic Bridge Minor mode(2)
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Primary regulator Regulators
Secondary Regulators Bridge Primary regulator Regulators
Secondary Regulators Bridge Primary regulator Regulators
Secondar y Regulators.
1. "X" means "don't care". 2. The description of these modes is in the following paragraph 9.7.
8.3
Basic device mode
The basic device mode is selected by leaving the GPIO[0] pin floating. In this mode S.A.B.Re doesn't use GPIO[3] and GPIO[4] as configuration pins, leaving them free for other uses. When in this mode the regulators included in the start up sequence (except VMAIN_SW) are considered as system regulators and they start in the following sequence: 1. 2. 3. 4. Auxiliary switching regulator1 (VAUX1_SW). Auxiliary switching regulator2 (VAUX2_SW). Main linear regulator (VMAIN_LIN). Main switching regulator (VMAIN_SW) (Not system regulator).
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Start-up configurations
8.4
Slave device mode
In slave device mode, S.A.B.Re consider the nAWAKE pin as an input enable. Since this is now a digital pin, the current pull up source inside the nAWAKE circuit is disabled. At the startup, if the nAWAKE pin is found to be low for a period higher than tAWAKEFILT seconds, S.A.B.Re enters directly in the "Low Power mode"; when nAWAKE pin is pulled high for a period higher than tAWAKEFILT seconds, S.A.B.Re begins its start up procedure.
8.5
Master device mode
In master device mode, S.A.B.Re begins its start up procedure without waiting for any external enable signal and it uses GPIO[5] pin to drive the nAWAKE pin of Slave devices. During the whole start up time, it forces its GPIO[5] pin at logic level "0" in order to maintain all slave devices in "Low Power mode" as previously described. When start up operations are completed, S.A.B.Re forces the GPIO[5] output to logic level "1" to enable the slave devices and keeps GPIO[5] output at high level until it senses an under-voltage on any of its System regulators. If firmware writes in the PwrCtrl register to set Master S.A.B.Re in "Low Power mode" it immediately forces GPIO[5] output to logic level "0" to force the slave devices to enter in "Low Power mode", then it waits for TMASTWAIT time and it starts its "Low Power mode" sequence.
8.6
Single device mode
In single device mode, the device behaves similarly to master device mode but: 1. 2. It doesn't use the GPIO[5] pin to drive slave devices. It doesn't wait for TMASTWAIT before entering in "Low Power mode".
8.7
Sub-configurations for slave, master or single device modes
Each slave, master or single device modes can be divided in other minor modes depending on the start-up sequence needed for S.A.B.Re internal regulators. Unless otherwise specified, in all the following modes the regulators included in the start up sequence are considered system regulators and they start in the sequence indicated.
8.7.1
Bridge mode
In this configuration bridges 3 and 4 are not used as regulators and therefore can be configured by the firmware in any of their possible bridge modes. When in this mode the power-up sequence is: 1. 2. Main switching regulator (VMAIN_SW). Main linear regulator (VMAIN_LIN).
8.7.2
Primary regulator mode (KP)
In this configuration bridge 4 can be configured by firmware while bridge 3 is configured as two separate synchronous switching regulators. The last regulator in the sequence (VAUX2_SW).is not considered a system regulator.
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Start-up configurations When in this mode the power-up sequence is: 1. 2. 3. Auxiliary switching regulator1 (VAUX1_SW).
S ABRE -LL-I
Main switching regulator (VMAIN_SW) together with main linear regulator (VMAIN_LIN). Auxiliary switching regulator2 (VAUX2_SW) (Not system regulator).
8.7.3
Regulators mode
In this configuration bridge 4 can be configured by firmware while bridge 3 is configured as two separate synchronous switching regulators, but the start up sequence is different previous one. When in this mode the power-up sequence is: 1. 2. 3. Main switching regulator (VMAIN_SW). Auxiliary switching regulator1 (VAUX1_SW) Auxiliary switching regulator2 (VAUX2_SW)
8.7.4
Simple regulator mode (KT)
Also in this configuration Bridge 4 can be configured by firmware while Bridge3 is configured as two separate synchronous switching regulators. The last regulator in the sequence (VMAIN_SW).is not considered a system regulator. When in this mode the power-up sequence is: 1. 2. 3. 4. Auxiliary switching regulator1 (VAUX1_SW). Auxiliary switching regulator2 (VAUX2_SW) Main linear regulator (VMAIN_LIN) Main switching regulator (VMAIN_SW) (not system regulator).
8.7.5
Bridge+ VEXT mode
In this configuration bridges 3 and 4 are not used as regulators and the regulator obtained using the switching regulator controller (VEXT) is included in start-up. When in this mode the power-up sequence is: 1. 2. 3. Main switching regulator (VMAIN_SW). Switching regulator controller regulator (VEXT). Main linear regulator (VMAIN_LIN).
8.7.6
Secondary regulators mode
In this configuration, bridge 3 is configured as a single synchronous switching regulator using its two half bridges in parallel (VAUX_(1//2)SW). When in this mode the power-up sequence is: 1. 2. 3. Main switching regulator (VMAIN_SW). Auxiliary switching regulator (VAUX(1//2)_SW). Main linear regulator (VMAIN_LIN).
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Power sequencing
9
9.1
Power sequencing
Overview
As soon as VSupply and VSupplyInt are above their power on reset level, S.A.B.Re will start the charge pump circuit; once VPump voltage reaches its under voltage rising threshold, S.A.B.Re begins a sequence that starts the regulators considered system regulators. A regulator is considered a System regulator if: It has to start in on state without any user action. It is included in the power-up sequence. Its under-voltage event is considered by S.A.B.Re as an error condition to be signaled through nRESET pin.
Once VSupply and VSupplyInt, VPump and all the system regulators are over their under voltage rising threshold, S.A.B.Re enters in the normal operating state, that will release nRESET pin and will wait for SPI commands. S.A.B.Re will reduce the noise introduced in the system by switching out of phase all its power circuits (switching regulators, bridges and charge pump). The S.A.B.Re's startup sequence of operation is the following: star t V3v3 internal linear regulator sample startup configuration wait enable if slave device star t charge pump star t system regulators (see order in Section 8.7) send enable to slave device, if master wait until VGPIO_SPI becomes ok
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Power saving modes
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10
10.1
Power saving modes
Overview
Saving power is very important for today platforms: S.A.B.Re implements different functions to achieve different levels of power saving. Sections here below describe these different power saving modes.
10.2
Standby mode
Almost all low voltage circuitry inside S.A.B.Re are powered by V3v3 internal regulator; this regulator is a linear regulator powered by VSupplyInt. This means that all the current provided by V3v3 regulator is directly coming from VSupplyInt and therefore the total power consumption is: Low voltage power = VSupply* IV3v3. because VSupplyInt is feeded by VSupply, directly or with a resistor in series. This power could be reduced by using a switching buck regulator to supply V3v3: in this case, assuming the buck regulator efficiency near to 100%, the dissipated power would become: Low voltage power 3.3V * IV3v3. To achieve this result there is the need to switch off the internal V3v3 linear regulator and to use an additional pin to provide a 3.3V supply to internal circuits. S.A.B.Re can do this by using the low voltage switch implemented on GPIO6 pin. This switch internally connects VGPIOSpi voltage to GPIO6 output so, by externally connecting GPIO6 to V3v3 pin, the VGPIOSpi voltage can be provided to low voltage circuitry inside S.A.B.Re. Figure 5. Standby mode function description
VSupplyInt VGPIOSpi
StdByMode
Power Switch 1
GPIO6 External connection 3.3V
3.3 V 1.9 V
0 + 1
V3v3 Regulator
-
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Power saving modes The StdByMode bit used to switch off V3v3 and switch on the power switch can be set to `1' by writing the standby command in the StdByMode register. S.A.B.Re exits standby mode if a reset event happens or "Low Power mode" is selected. Because all internal low voltage circuitry powered by V3v3 are designed to work with a 3.3V voltage rail, when the standby mode is used, VGPIOSpi is requested to be at 3.3V.
10.3
Hibernate mode
S.A.B.Re's hibernate mode allows the firmware to switch off some (or all) selected System Regulators leaving in on state only those necessary to resume S.A.B.Re to operative condition when waked-up by an external signal. Hibernate mode is selected when the firmware writes the command word in the HibernateCmd register. When in hibernate mode S.A.B.Re will force regulators in the state (on/off) selected by the firmware by writing in the HibernateCmd register and will force nRESET pin low. The exiting from hibernate mode is achieved by forcing at low level nAWAKE pin (or GPIO5 pin if S.A.B.Re is in Slave mode); S.A.B.Re will also exit from hibernate mode if an undervoltage event happens on VSupply, VSupplyInt, VPump or V3v3. When the exit from hibernate mode is due to an external command, S.A.B.Re sets to `1' the bit HibModeLth in the HibernateStatus register.
10.4
Low power mode
When in normal operating mode, the microcontroller can place S.A.B.Re in "Low Power mode". In this condition S.A.B.Re sets all bridges outputs in high impedance, powers down all regulators (including system regulators and charge pump) and disables almost all its circuits including internal clock reducing as much as possible power consumption. The only circuits that remain active are: V3V3 internal regulator. nAWAKE pin current pull-up. nRESET pin that will be pulled low. POR circuit.
The entering in low power mode is obtained in different ways depending if S.A.B.Re is configured as slave device or not. When S.A.B.Re is configured as slave device the low power mode is directly controlled by nAWAKE pin that acts as an enable: if this pin is low for a time longer then tAWAKEFILT, Low Power mode is entered; if this pin is high S.A.B.Re exits from Low Power mode. In all other start-up configurations, Low Power mode is entered by writing a Low Power mode command in the PowerModeControl register; once S.A.B.Re is in Low Power mode it starts checking the nAWAKE pin status: if it is found low for a time longer than tAWAKEFILT, S.A.B.Re exits from Low Power mode and restarts its startup sequence. When the nAWAKE pin is externally pulled low, the "AWAKE" event is stored and it is readable through SPI. S.A.B.Re will also exit from Low Power mode if a POR event is found. Note: When in "Low power mode" VSupply is monitored only for its power on reset level.
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Power saving modes
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10.5
nAWAKE pin
At the start up, before S.A.B.Re has identified the required operation mode (see Chapter 8), a current sink IINP is always active to pull down nAWAKE pin. As soon as the operation mode (basic, slave, master or single device) is detected, the functionality of nAWAKE pin will be different. If S.A.B.Re is not configured as Slave device a current source IOUT will be active on this pin, while the current sink IINP will be disabled. If S.A.B.Re is configured as a Slave device, the current sink IINP will be active until nAWAKE pin is detected high for the first time; after that both current sources IINP and IOUT will be disabled and the nAWAKE pin can be considered as a digital input. Here below is reported the nAWAKE pin simplified schematic. Figure 6. nAWAKE function block diagram
V 3v3 SlaveMode I OUT
AWAKE_req
AWAKE nAWAKE seen high for the first time after start up.
I INP
Table 16.
Parameter VIL VIH VHYS IOUT IINP tAWAKEFILT
nAWAKE function specifications
Description nAWAKE logic low threshold nAWAKE logic high threshold nAWAKE input hysteresys nAWAKE pin output current nAWAKE pin input current Filter time nAWAKE=0V(1) nAWAKE=0.8V
) (1
Test condition
Mi n
Typ
Ma x 0.8
Unit V V
1.6 0.25 - 0.72 0.2 1.2 -2 0.4
V mA mA ns
1. Current is defined to be positive when flowing into the pin.
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Linear main regulator
11
11.1
Linear main regulator
Overview
The linear main regulator is directly powered by VSupply voltage and it is one of the regulators that S.A.B.Re could consider as a system regulator. This means that the voltage generated by this regulator is not used to power any internal circuit, but S.A.B.Re will check that the feedback voltage VLINmain_FB is in the good value range before enabling all its internal functions. When an under-voltage event (with a duration longer than period Tlinear_uv defined by the deglitch filter) is detected during normal operation, S.A.B.Re will enter in reset state and it will signal this event to the microcontroller by pulling low the nRESET pin and disabling most of its internal blocks. Here are summarized the primary features of the regulator: Regulated output voltage from 0.8V to VSupply-2V with a maximum load of 10mA. Band gap generated internal reference voltage. Shor t circuit protected (output current is clamped to 22mA typ). Under voltage signal (both continuous and latched) accessible through serial interface. Low power dissipation mode.
The internal series element is a P-channel MOS device. The voltage regulator will regulate its output so that feedback pin equals VLINmain_FB, therefore the regulated voltage can be calculated using the formula: VLINmain_OUT = VLINmain_ref *(Ra+Rb)/Rb Figure 7. Linear main regulator
V supply
Body Diode
V LINmain_OUT
Driver
Cc
+ -
Ra
V LINmain_FB V LINmain_ref
Rb
To extend the output current capability this regulator can be used as a controller for an external active component able to provide higher current (i.e. a Darlington device); the external power element allows the handling of an higher current since it dissipates the
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power externally (the power dissipated by a linear driver supplied at VSupply and regulating a voltage VLINmain_OUT with an output current IOUT is about: Pd= (VSupply-VLINmain_OUT)*IOUT. Figure 8. Linear main regulator external bipolar example
V supply
Body Diode VLINmain_OUT Cc
Driver
Cload
+ VLINmain_FB VLINmain_Ref
Ra
Rb
Whichever configuration is used (regulator or controller), a ceramic capacitor must be connected on the output pin towards ground to guarantee the stability of the regulator; the value of this capacitance is in the range of 100nF to 1F depending on the regulated voltage. When this regulator is disabled, the whole circuit is switched off and the current consumption is reduced to a very low level both from V3v3 and from VSupply. When in this condition, the output pin is pulled low by an internal switch. Table 17. System linear regulator operating specifications
Description Output pin voltage range Drop out voltage Internal switch pull down current Feedback pin voltage range Feedback reference voltage Feedback pin input current Test condition
(1)
Parameter VLINmain_OUT Vdrop
Min 0 2
Typ
Max VSupply
Unit V V
Vdrop= Vsupply-VLINmain_OUT Linear Main Regulator disabled; VLINmain_OUT=1V
IPD
3
mA
VLINmain_FB VLINmain_Ref ILINmain_Ref
0 0.776 -2 0.8
3.6 0.824 2
V V A
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SABRE-LL-I Table 17.
Linear main regulator System linear regulator operating specifications (continued)
Description Maximum Output current Output short circuit current Load regulation Line regulation Loop voltage accuracy Under voltage falling threshold Under voltage rising threshold Under voltage hysteresis Under voltage deglitch filter VLINmain_OUT =0.8V 0.8V 5V
(3)
Parameter IoutLinMax Ishort Vout/Vo Vout/VSupply Vloop_acc VuvFall VuvRise Vuvhys tprim_uv
Test condition Regulated voltage = Vsupply-2V VLINmain_OUT =0V, VLINmain_FB =0V 0 Iload IoutLinMax(2) Iload =10mA
(2)
Min 10 12
Typ
Max
Unit mA
24 0.8 0.2 2.5
mA % % % 89.5 95.5 % % % us
84.5 90.5
87 93 6 5 1 0.68 0.33 0.1
(3)
(3)
CC
Compensation capacitance
F
1. The external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range. 2. Load regulation is calculated at a fixed junction temperature using short load pulses covering all the load current range. This is to avoid change on output voltage due to heating effect. 3. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VLINmain_Ref).
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Main switching regulator
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12
12.1
Main switching regulator
Overview
Main switching regulator is an asynchronous switching regulator intended to be the source of the main voltage in the system. It implements a soft start strategy and could be a system regulator so even if its output voltage VMAIN_SW is not used to power any internal circuit, S.A.B.Re will check that it is in the good value range before enabling all its internal functions. When S.A.B.Re detects a system regulator under-voltage event with a duration longer than the period defined by the deglitch filter (Tprim_uv), it will enter in reset state signaling this event to the microcontroller by pulling low the nRESET pin and disabling most of its internal block (e.g. bridges, GPIOs, ...). The output voltage will be externally set by a divider network connected to feedback pin. To reduce as much as possible the regulation voltage error S.A.B.Re has the possibility to choose between four feedback voltage references (and, as a consequence, four undervoltage thresholds) using the serial interface. The feedback reference voltage selection is made by writing the SelFBRef bits in the MainSwCfg register according to the table here below: Table 18. Switching regulator controller PWM specification
Reference voltage (VFBREF) Min 0.776 0.97 2.425 2.910 Typ 0.8 1 2.5 3 Max 0.824 1.03 2.575 3.09 V V V V Default state Unit Comments
MainSwCfg register SelFBref[1] 0 0 1 1 SelFBref[0] 0 1 0 1
Reference voltage range can be changed by using a metal layer change in order to adapt them to customer system. Here after are summarized the primary features of this regulator: Internal power switch. Soft start circuitry to limit inrush current flow from primary supply. Internally generated PWM (250kHz switching frequency). Nonlinear pulse skipping control. Protected against load short circuit. Cycle by cycle current limiting using internal current sensor. Under voltage signal (both continuous and latched) accessible through SPI.
When S.A.B.Re is in "Low Power mode", this regulator will be disabled. In order to save external components and power when using two or more S.A.B.Re IC's on the same board, the primary switching regulator can be disabled by serial interface. Care must be paid using this function because an under-voltage on this regulator, as previously seen, will be read as a fault condition by S.A.B.Re.
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Main switching regulator
12.2
Pulse skipping operation
Pulse skipping is a well known, non linear, control strategy used in switching regulators. In this technique (see Figure 9) the feedback comparator output is sampled at the beginning of each switching cycle. At this time, if the sampled value shows that output voltage is lower than requested one, the complete PWM duty cycle is applied to power switch; otherwise no PWM is applied and the switching cycle is skipped. Once PWM is applied to power element only a current limit event can disable the power switch before the whole duty cycle is finished. Figure 9. Main switching regulator functional blocks
VSupply
Current Sense
Charge pump Voltage
High Side Driver
VSWmain_SW
La Ra C
Voltage From Central Logic
Control Logic
Regulator Freq
Loop Control
+
VSWmain_FB
Rb
Regulator Ref
Under voltage flag
Filter
To Central Logic
+
Under voltage Threshold
In pulse skipping control the duty cycle must be chosen by the user depending on supply voltage and output regulated voltage. Therefore the switching regulator has 4 possible duty cycles that can be changed by writing the VmainSwSelPWM bits in the MainSwCfg register according to following table. Table 19. Main switching regulator PWM specification
Duty cycle value Comments VmainSwSelPWM[1:0] 00 01 10 11 Typical 12% 15% 26% 63.5% Default state
MainSwCfg register
Adjustable duty cycles can be changed by a metal layer change in order to adapt it to customer system. The only limitation is that all regulators share the same duty cycle bus, so any modification must consider all regulators duty cycles.
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The output current is limited to a value that can be set by means of selilimit bit in the MainSwCfg register according to following table: Table 20. Main switching regulator current limit
Current limit (min) 3.3A 2.3A Comments Default state
SelIlimit 0 1
Table 21.
Parameter
Main switching regulator specifications
Description Test condition
(1)
Min -1 -40 -15 -10 0.8 0.002
Typ
Max Vsupply +40 +5 +0 5 3 0.55
Unit V A A A V A O
VMAIN_SW Output pin voltage range IQ IQlp IQfb Vout Iload RonH Vloop VregR Output leakage current Output leakage current in "Low Power Mode" Feedback pin current Output voltage range Output load current Internal high side RDson Loop voltage accuracy Output voltage ripple (RMS) Under voltage falling threshold Under voltage rising threshold Under voltage hysteresys Under voltage deglitch filter Current limit protection Current limit deglitch time Current limit response time Current limit response time in UV condition. Switching output rise time Switching output fall time Operating frequency
Tjunction = 125C VSupply = 36V Tjunction = 125C Tjunction = 125C
(2)
VSupply = 36V Iload=1A Tjunction = 125C
3% L =150u, C=330F/ESR=0.54
(3) (4)
28
mVRMS
VuvFall VuvRise Vuvhys tprim_uv Ilimit tdeglitch tI_lim tI_limUV tr tf FregPwm
84.5 90.5
87 93 6 5
89.5 95.5
% % % us
(4)
SelIlimit ="0" SelIlimit ="1"
3.3 2.3 50
5 3.5
TBD TBD
A A ns
In normal operating mode (no UV)(5) When in Under Voltage(6) VSupply = 36V, Resistive load to gnd = 422 (7) VSupply = 36V, Resistive load to gnd = 10 (7) 5 5 Fosc/64
650 400 30 30
ns ns ns ns kHz
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Main switching regulator
1. The external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range. 2. The regulated voltage can be calculated using the formula: VMAIN_SW = VFBREF *(Ra+Rb)/Rb. 3. The choice of proper values for L and C depends from the application. 4. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VSW_main_FB). 5. This condition is intended to simulate an extra current on output. 6. This condition is intended to simulate a short circuit on output. 7. Rise time is measured between 10% and 90% of supply voltage.
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Switching regulator controller
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13
13.1
Switching regulator controller
Overview
This circuit controls an external FET to implement a switching buck regulator using a non linear pulse skipping control with internally generated PWM signal. The output voltage will be externally set by a divider network connected on feedback pin. To reduce as much as possible the regulation voltage error S.A.B.Re has the possibility to switch between four regulator feedback voltage references (and, as a consequence, four under-voltage thresholds) using serial interface. The feedback reference voltage is selected by writing the SelFBRef bits in the SwCtrCfg register according to the following table. Table 22. Switching regulator controller PWM specification
Reference voltage (VFBREF) Min 0.776 0.970 2.425 2.910 Typ 0.8 1 2.5 3 Max 0.824 1.030 2.575 3.09 V V V V Default state Unit Comments
SwCtrCfg register SelFBref[1] 0 0 1 1 SelFBref[0] 0 1 0 1
Adjustable feedback voltages can be changed using a metal layer change in order to adapt it to customer system. This regulator is switched off when S.A.B.Re is powered up for the first time and can be enabled using S.A.B.Re's SPI interface. Here after are summarized the main features of the regulator: Soft start circuitry to limit inrush current flow from primary supply. Changeable feedback reference voltage Internally generated PWM (250kHz switching frequency). Nonlinear pulse skipping control. Protected against load short circuit. Cycle by cycle current limiting using internal current sensor. Under voltage signal (both continuous and latched) accessible through SPI.
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SABRE-LL-I Figure 10. Switching regulator controller functional blocks
Switching regulator controller
V supply
Rsense
CurrentSense Charge pump Voltage
V SWDRW_sns N-CH Fet V SWDRV_gate V SWDRV
Voltage Loop Control
Driver La Ra C V SWDRV
FB
SW
V out
From Central Logic
Control Logic
Regulator Freq
+
SelFBRef1:0] [
Analog Mux
Vref = 3 V Vref = 3V Vref=0.8V Vref=0.8V
Rb
VFBRef
undervoltage flag
Filter
+
To Central Logic SelFBRef Uv Threshold 1
Analog Mux
Uv Threshold 2
Under voltage Threshold
13.2
Pulse skipping operation
Pulse skipping strategy has already been explained on main switching regulator section. This regulator has 4 possible PWM duty cycles that can be changed writing in the SelSwCtrPWM bits in the SwCtrCfg register using SPI. Table 23. Switching regulator controller PWM specification
Duty cycle value Comments SelSwCtrPWM[1:0] 00 01 10 11 Typical 9% 12% 22.5% 58% Default state
SwCtrCfg register
Adjustable duty cycles can be changed using a metal layer change in order to adapt it to customer system. The only limitation is that all regulators share the same duty cycle bus, so any modification must consider all regulators needed duty cycles.
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13.3
Output equivalent circuit
The switching regulator controller output driving stage can be represented with an equivalent circuit as in the figure below: Figure 11. Switching regulator controller output driving equivalent circuit
VPUMP
I SOURCE
Source command Tsink Sink pulse command RSUSTAIN Sink command I SINK V SWDRV_SW V SWDRV_gate
As can be seen from the above figure, the external switch gate is charged with a current generator ISOURCE and it is discharged towards ground with a current generator ISINK that is applied for a TSINK pulse while an equivalent resistor RSUSTAIN is connected between gate and source until the sink command is present. The table here below lists the values of the above mentioned parameters: Table 24.
Parameter ISOURCE I SINK t SINK RSUSTAIN
Switching regulator controller operating specification
Description Source current Sink current Sink discharge pulse time Gate-source sustain resistance (VSWCTR_GATE - VSWCTR_SRC) = 0.2V Test condition VPump=VSupply+12V VSWCTR_GATE=0V VSWCTR_GATE = VSupply Min Typ 25 20 600 650 Max 50 Unit mA mA ns
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Switching regulator controller
13.4
Switching regulator controller specifications
Table 25.
Parameter VSWDRV_SW VSWDRV_GAT
E
Switching regulator controller operating specification
Description VSWDRV_SW pin voltage range Gate drive pin voltage Test condition
(1)
Min -1 0 VSupply -3V
Typ
Max VSupply VPump VSupply
Uni t V V V V
VSWDRV_SNS Sense pin voltage Vvgs_ext IQ IQlp VSWDRV_FB Vloop VuvFall(1) Gate to source voltage for ext FET Output leakage current Output leakage current in "Low Power Mode" VSWDRV_FB pin current Loop voltage accuracy Under voltage falling threshold Under voltage rising threshold Under voltage hysteresys Under voltage deglitch filter Over current threshold voltage Current limit deglitch time Current limit response time Current Limit response time in UV condition. Operating frequency In normal operating mode (no UV)(2) When in Under Voltage(3) VSupply = 36V, Tjunction = 125C VSupply = 36V, Tjunction = 125C VSupply = 36V, Tjunction = 125C
VPump -15 -5 -10 3% 84.5 90.5 87 93 6 5 250 50 900 550 Fosc/6 4 300 350 89.5 95.5 +15 +5 +10
A A A
% % % us mV ns ns ns kHz
VuvRise(1) Vuvhys(1) tprim_uv Vovc tdeglitch tI_lim tI_limUV FregPwm
1. Under voltage rising and falling thresholds are referred to feedback pin voltage. 2. This condition is intended to simulate an extra current on output. 3. This condition is intended to simulate a short circuit on output.
13.5
Switching regulator controller application considerations
This controller can implement a step-down switching regulator used to provide a regulated voltage in the range 0.8V 32V. Such kind of variation could be managed by considering
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some constraints in the application and particularly by choosing the correct feedback reference voltage as indicated in the following table: Table 26. Switching regulator controller application feedback reference
Feedback voltage reference 0.8V - 1V 2.5V - 3V
Output regulated voltage range 0.8V Vout < 5V 5V Vout 32V
Typical application can be considered the following, supposing the external mosfet type STD12NF06L: Max DC current load = 3A Typ Over current threshold = 3A * 1.5 = 4.5A L = 150 H C = 220-330 F
In this conditions the step-down regulator will result over-load protected, short-circuit protected over all the regulated voltage range and the VSupply range. Other application configurations could be evaluated before being implemented.
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Power bridges
14
14.1
Power bridges
Overview
S.A.B.Re includes four H bridge power outputs (each one made by two independent half bridges) that are configurable in several different configurations. Each half bridge is protected against: over-current, over-temperature and short circuit to ground, to supply or across the load. When an over current event occurs, all outputs are turned off (after a filter time), and the over current bit is stored in the internal status register that can be read through SPI. Positive and negative voltage spikes, which occur when switching inductive loads, are limited by integrated freewheeling diodes (see Figure 12). Figure 12. H Bridge block diagram
High side Driver
High side Driver
Control Logic
Control Logic
Low side Driver
Low side Driver
During the start up procedure the bridges are in high impedance and after that they can be enabled through SPI. When a fault condition happens, i.e. an over-temperature event, the bridges return in their start-up condition and they need to be re-enabled from the micro controller. The bridges can use PWM signals internally generated or externally provided (supplied through the GPIO pins). Internally generated PWM signals will run at approximately 31.25kHz with a duty cycle that, through serial interface, can be programmed and incremented in steps of 1/(512*Fosc). To reduce the peak current requested from supply voltage when all bridges are switching, the four internally generated PWM signals are outof-phase. Each half bridge will use the PWM signal selected by the respective MtrXSelPWMSideY[1:0] (X stands for 1, 2, 3 or 4; Y stands for A or B) bits in the SPI, but if
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Power bridges
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two half bridges are configured as a full bridge, only the PWM signal chosen for side A will be used to drive the resulting H bridge. More in detail the PWM selection truth table will be as describe in the following tables: Table 27. PWM selection truth for bridge 1 or 2
Selected PWM(1) MotorXPWM (Configurable by means of MtrXCfg register). AuxXPWM (Configurable by means of AuxPwmXCtrl register). ExtPWM1 (from GPIO 9 input) ExtPWM2 (from GPIO 10 input)
MtrXSelPWMSideY [1] MtrXSelPWMSideY [0] 0 0 1 1 0 1 0 1
1. In this table X stands for 1 or 2, Y stands for A or B.
Table 28.
PWM selection truth for bridge 3 or 4
Selected PWM(1) MotorXPWM (Configurable by means of MtrXCfg register). AuxXPWM (Configurable by means of AuxPwmXCtrl register). ExtPWM3 (from GPIO 2 input) ExtPWM4 (from GPIO 11 input)
MtrXSelPWMSideY [1] MtrXSelPWMSideY [0] 0 0 1 1 0 1 0 1
1. In this table X stands for 3 or 4, Y stands for A or B.
Here below is reported a block diagram representing the possible PWM choices for each S.A.B.Re half bridges. The figure is related only to bridges 1 and 2, but it could be assumed to be valid also for bridges 3 and 4, with few differences due to different possible configurations of these last drivers.
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SABRE-LL-I Figure 13. Bridge 1 and 2 PWM selection
Power bridges
Mtr1SelPWMSide [1:0] A 00 Motor1 PWM 01 Aux1PWM 10 ExtPWM1 11 ExtPWM2 Mtr1_2Parallel Mtr1SelPWMSideB [1:0] Mtr1Tablel[1:0] 00 Motor1 PWM 01Aux1PWM 10ExtPWM1 11ExtPWM2
Side B Power Section Side A Power Section Side B Power Section Side A Power Section
Motor 1 side A Logic Table
Motor 1 sideB Logic Table
Bridge 1
Mtr1_2Parallel
Mtr2SelPWMSide [1:0] A Mtr2Tablel[1:0] 00 Motor2 PWM 01Aux2Pwm 10ExtPwm1 11ExtPwm2 Mtr2SelPWMSide [1:0] A 00 Motor2 PWM 01 Aux2Pwm 10 ExtPwm1 11 ExtPwm2 Mtr1_2Parallel Mtr2Tablel[1:0]
Motor 2 side A Logic Table
Motor 2 sideB Logic Table
Bridge 2
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Power bridges
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14.2
Power bridges operating specifications
Table 29.
Parameter RON_1_2 RON_3_4 I Max I Max I dss IQlp
Power bridges operating specifications
Description Bridge 1 and 2 diagonal Ron Bridge 3 and 4 diagonal Ron Bridge 1 and 2 max operative current Bridge 3 and 4 max operative current Output leakage current. Output leakage current in "Low Power Mode" Tjunction = 125C VSupply = 36V, Tjunction = 125C MtrXSideYILimSel[1:0]=00 MtrXSideYILimSel[1:0]=01 MtrXSideYILimSel[1:0]=10 MtrXSideYILimSel[1:0]=11(2) MtrXSideYILimSel[1:0]=00 MtrXSideYILimSel[1:0]=01 MtrXSideYILimSel[1:0]=10 MtrXSideYILimSel[1:0]=11(2) -5 0 -10 0.6 1.4 2.4 2.4 0.7 1.5 2.5 2.5 Test condition I = 1.4A, VSupply = 36V, Tjunction = 125C I = 1A, VSupply = 36V, Tjunction = 125C Min Typ Max Unit 1.0 1.5 2.5 1.5 +50 +10 1.6 2.6 3.6 3.6 1.7 2.7 3.7 3.7 2.5 2.5 5 5 MtrXIlimitOffTimeY[1:0]=00 MtrXIlimitOffTimeY[1:0]=01 MtrXIlimitOffTimeY[1:0]=10 MtrXIlimitOffTimeY[1:0]=11(5) VSupply = 36V, Resistive load between outputs: R= 25 Ohm(6) VSupply = 36V, Resistive load between outputs: R= 36 Ohm(6) VSupply = 36V, Resistive load between outputs: R= 25 Ohm(6) 100 60 120 240 480 250
A A A A
IprotL_1&2
Low side current protection for bridges 1 & 2(1)
A
IprotH_1&2
High side current protection for bridges 1 & 2(1)
A
Iprot_3 Iprot_4 tfilter tdelay
Low side current protection for bridges 3 & 4(1) High side current protection for bridges 3 & 4(1) Current limit filter time Current limit delay time
MtrXSideYILimSel[1:0]=11(3)(4) 1.55 MtrXSideYILimSel[1:0]=11(3)(4) 1.6 2
A A us us ns ns ns ns ns
toc_off
Over current off time
tr1_2
Output rise time bridges 1 &2 Output rise time bridges 3 & 4 Output fall time bridges 1 & 2
tr3_4
50
200
ns
tf1_2
100
250
ns
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SABRE-LL-I Table 29.
Parameter
Power bridges Power bridges operating specifications (continued)
Description Output fall time bridges 3 & 4 Anti crossover rising dead time Anti crossover falling dead time Operating frequency Delay from PWM to output transition Test condition VSupply = 36V, Resistive load between outputs: R= 36 Ohm(6) Min Typ Max Unit
tf3_4
50
250
ns
tdeadRise tdeadFall Fpwm tresp
100 100 Fosc /512 500
450 450
ns ns kHz ns
1. The current protection values must be intended as a protection for the chip and not as a continuous current limitation. The protection is performed by switching off the output bridge when current reaches values higher than the Iprot max. No protection could be guaranteed for values in the middle range between Ioperative max and Iprot. 2. In this cell X stands for 1 or 2, Y stands for A or B 3. In this cell X stands for 3 or 4, Y stands for A or B 4. The current protection thresholds for Bridge 3 and 4 are not selectable so only the max current value (MtrXSideYILimSel[1:0]= 11) is available. 5. Over Current Off time can be configured using SPI. 6. Rise and fall time are measured between 10% and 90% of supply voltage. With device in full bridge configuration (resistive load between outputs).
14.3
Possible configurations
The selection of the bridge configuration is done through SPI, by writing the MtrXTable[1:0] bits in the MtrXCfg register. The table below shows the correspondence between MtrXTable[1:0] bits and the bridge configuration. Table 30. Bridge selection truth
MtrXTable[0] 0 1 0 1 Bridge truth Full bridge configuration High or low side switch configuration Half bridge configuration High or low side switch configuration
MtrXTable[1] 0 0 1 1
Bridge 1 & 2 can be paralleled by means of Mtr1_2Parallel bit in the Mtr1_2Cfg register: Bridge 1 and 2 paralleled will form superbridge1, bridge X side A and bridge X side B paralleled form SuperHalfBridgeX or SuperSwitchX. Bridge 3 & 4 can be configured by means of Mtr3_4CfgTable[1:0] bits in the Mtr3_4Cfg register according to following table:
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Power bridges Table 31. Bridge 3 and 4 configuration
Mtr3_4CfgTable[0] 0 1 0 1
S ABRE -LL-I
Mtr3_4CfgTable[1] 0 0 1 1
Bridge 3 and 4 configuration Two independent bridges Two bridges in parallel Stepper motor Stepper motor
The possible configurations for the bridges are described in the following:
14.3.1
Full bridge
When in full bridge configuration, the drivers will behave according to the following truth table: Table 32.
TSD 1 0 0 0 0 0 0 0 0 0 0
Full bridge truth
Low power mode X X 1 0 0 0 0 0 0 0 0 Enable X X X 0 1 1 1 1 1 1 1 Current MtrXCtrl MtrXCtrl limit SideA SideB X X X X 1 0 0 0 0 0 0 X X X X X 0 0 0 1 1 1 X X X X X 0 1 1 0 0 1 PWM X X X X X X 0 1 0 1 X OUT+ Z Z Z Z Z 0 1 0 1 1 1 OUTZ Z Z Z Z 0 1 1 1 0 1
nRESET X 0 1 1 1 1 1 1 1 1 1
Note: When "Low Power mode" is active, the bridges will enter in low power state and will reduce its biasing thus contributing to the power saving. When a current limit event occurs this event will be latched and the bridges will remain in high impedance state for the toff time.
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Power bridges
14.3.2
Parallel configuration (super bridge)
Bridges 1, 2, 3 and 4 can be configured to be used two by two (1 plus 2, 3 plus 4) as one super bridge thus enabling the driving of loads (motors) requiring high currents. In this configuration the half bridges will be paralleled and will work as one phase of the superbridge just created: the two phases + will become phase + of the newly created superbridge while the two phases - will become phase . Figure 14. Super bridge configuration
Parallel Full Bridge
Super Bridge
Bridge 1 (3)
PH PH
Bridge 2 (4)
PH
PH
+
-
-
+
M
When this configuration is chosen for bridges 1 (3) and 2 (4), the resulting bridge will use the driving logic of bridge 1 (3) so for programming it must be used the bridge 1 (3) control and status bits (direction, PWM, ...): i.e. the used PWM signal will be chosen by Mtr1SideAPwmSel[1:0] (Mtr3SideAPwmSel[1:0]) bits in SPI. If the bridges are not configured to be used in parallel, each side of the bridge will use the PWM selected by the respective MtrXPWMYSel[1:0] bits in the SPI, but if one of the two drivers is configured as a full bridge only one of the two selected PWM will be used to drive the motor and this is the PWM chosen for side A. In order to avoid any problem coming from different propagation times of PWM signals the anti-crossover dead times are slightly increased when the bridges are paralleled.
14.3.3
Half bridge configuration
Each bridge can be configured to be used as 2 independent half bridges or as 1 super half bridge (see Figure 15). It is also possible to parallel more than one bridge and use all of them as a single super half bridge.
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Power bridges Figure 15. Half bridge configuration
S ABRE -LL-I
V Supply
V pump
High side Driver
Control Signals From SPI
DCX Phase output
Control Logic
In this case each half bridge will behave according to the following truth table. Table 33.
TSD 1 0 0 0 0 0 0 0 0
Half bridge truth
nReset X 0 1 1 1 1 1 1 1 Low power mode X X 1 0 0 0 0 0 0 Enable X X X 0 1 1 1 1 1 Current limit X X X X 0 0 0 0 1 MtrXCtrl SideA/B X X X X 0 0 1 1 X PWM X X X X 0 1 0 1 X OUT Z Z Z Z Z 0 Z 1 Z
Note: When "Low Power mode" bit is active the bridges will reduce its biasing thus contributing to the power saving. When a current limit event occurs this event will be latched and the bridges will remain in high impedance state for the toff time.
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Signals
Low side Driver
Fault
SABRE-LL-I
Power bridges
14.3.4
Switch configuration
Each bridge can be configured to be used as 2 independent switches that connects the output to supply or to ground. It is also possible to parallel the two switches and use them as a single super switch. All resulting switches will behave according to the following truth table. Table 34.
TSD 1 0 0 0 0 0 0 0
Switch truth
nReset X 0 1 1 1 1 1 1 Low power mode X X 1 0 0 0 0 0 Enable X X X 0 1 1 1 1 Current limit X X X X 0 0 0 1 MtrXCtrl SideA/B X X X X 0 1 1 X PWM X X X X X 0 1 X OUT Z Z Z Z Z 1 0 Z
Note: When "Low Power mode" bit is active the bridge will reduce its biasing thus contributing to the whole power saving. When a current limit event occurs this event will be latched and the bridge will remain in high impedance state for the toff time.
14.3.5
Bipolar stepper configuration
The bridges 3 and 4 can be configured to be used as a micro-stepping, bidirectional driver for bipolar stepper motors. The primary features of the driver are the following: Internal PWM current control. Micro stepping. Fast, mixed and slow current decay modes.
Each H-bridge is controlled with a fixed and selectable off-time PWM current-control circuit that limits the load current to a value set by choosing VSTEPREF voltage by means of the internal DAC and an the external RSENSE value. The max current level could be calculated using the formula: IMAX=VSTEPREF/RSENSE To obtain the best current profile, the user can choose three different current decay modes: slow, fast and mixed. Initially, during Ton, a diagonal pair of source and sink power MOS is enabled and current flows through the motor winding and the sense resistor. When the voltage across the sense resistor reaches the programmed DAC output voltage, the control logic will change the status of the bridge according to the selected decay mode (slow, fast or mixed). In slow decay mode the current is recirculated through the path including both high side power MOS for the whole toff time. In fast decay mode the current is recirculated through the high and low side power MOS opposite respect to those forcing current to
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Power bridges
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increase. Mixed decay mode is a selectable mix of the previous two modes (fast decay followed by slow decay) and allows the user to find the best trade off between load current ripple and fast current levels transition. Additionally, by setting the SeqMixedOnlyInDecreasingPh bit in the StpCfg1 register, the user can choose to apply the fast decay percentage in mixed mode always or only when the current is decreasing (i.e from 90 to 180 and from 270 to 360 of the sinusoidal wave). By using SPI interface the user can choose:
Control type (external firmware control, half step, normal drive, wave drive, micro-step). Up to 16 current levels (quasi-sinusoidal increments) for each bridge. Current direction. Decay mode. Blanking time. Off time (32 values from 2s to 64s). Percentage of fast decay respect to toff (when in mixed decay mode).
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SABRE-LL-I Figure 16. Bipolar stepper configuration
Power bridges
DC3_PHDC3SENSE
V supply
DC3_PH+
Stepper Motor
VRefA
Supply
DC4 PHSupply
PH-
PH+
PH-
PH+
DC4 PH+
Sense
Sense
Bridge Driver
- Control Logic - Toff generation - DAC reference selection
Bridge Driver
Ref1 V STEPREF Ref2 VRefA
VRefB
DC4SENSE
StepperDACPhA SelStepRef StepperDACPhB VRefB
The operating characteristics remain the same (when applicable) already seen in the power bridges operating specifications with the addition of the following: Table 35.
Parameter VSTEPREF Sense_off
Stepper specifications
Description Reference voltage Sense comparator offset Test condition SelStepRef =0 SelStepRef =1 Min Typ Max 0.520 0.780 12 Unit V mV
0.480 0.50 0.720 0.75 -12
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Power bridges
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Using the StepCtrlMode[2:0] bits in StepCfg1 register, S.A.B.Re can be programmed to internally generate the stepping levels. In these cases and depending on the StepFromGpio bit in the StpCfg1 register the Stepper driver will move to next step each time the StepCmd bit is set at logic level "1" or at each pulse transition longer than ~1s externally applied on GPIO12 (StepReq signal), according to following table: Table 36. Sequencer drive
StepFromGpio 0 1 Sequencer driven by StepCmd bit in StepCmd register. GPIO12 input pin.
The allowable control modes are as follows: 1. 2. Stepping sequence left to external microcontroller: in this mode the current level in each motor winding is set by the microcontroller via the serial interface. Full step: in this mode the electrical angle will change by 90 steps at each StepReq signal transition. There are two possibilities: Normal step (two phases on): in normal step mode both windings are energized simultaneously and the current will be alternately reversed. The resulting electrical angles will be 45, 135, 225 and 315. Wave drive (one phase on): In wave drive mode each winding is alternately energized and reversed. The resulting electrical angles will be 90, 180 and 270 and 360.
3.
Half step: in this mode, one motor winding is energized and then two windings alternately so the electrical angles the motor will do when rotating in clockwise direction and using the same current limit in both the phases are: 45, 90, 135, 180, 225, 270, 315 and 360. Microstepping: in this mode the current in each motor winding has a quasi sinusoidal profile. The increment between each step is obtained at each transition of StepCmd bit in StepCmd register. The difference between each step could be chosen (4, 8 or 16 levels for each phase) according to following table: Stepper mode
Control mode No Control Half Step Normal Step Wave Drive 1/4 Step 1/8 Step 1/16 Step Description Stepping sequence control left to the external controller Half step Full step (two phases on) Full step (one phase on) Four micro steps Eight micro steps Sixteen micro steps
4.
Table 37.
StepCtrlMode[2:0] 000 or 111 001 010 011 100 101 110
Note: When in 1/16 step mode, the best phase approximation of sinusoidal wave, is obtained by repeating the "F" step as follows: 0, 1, 2, 3, ... , D, E, F, F, F, E, D, ... , 3, 2, 1, 0
When internal stepping sequence generation is used, the stepping direction is set by the StepDir bit according to the following table.
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SABRE-LL-I Table 38. Stepper sequencer direction
StepDir 0 1 Direction Counter Clockwise (CCW) Clockwise (CW)
Power bridges
Note: It is intended as clockwise the sequence that forces a clockwise rotation of the versors representing the current module and phase.
An internal DAC is used to digitally control the output regulated current. The available values are chosen to provide a quasi sinusoidal profile of the current. The current limit in each phase is decided by PhADAC[3:0] bits for phase A and PhBDAC[3:0] bits for phase B. The table below describes the relation between the value programmed in the stepper DAC and the current level: Table 39. DAC
Phase Current ratio respect to IMAX PhXDAC [3:0] Min 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 7.8 17.5 27.0 36.3 45.1 53.6 61.4 68.7 75.3 81.1 86.2 90.4 93.7 96.5 Typ (Hi-Z) 9.8 19.5 29.0 38.3 47.1 55.6 63.4 70.7 77.3 83.1 88.2 92.4 95.7 98.1 IMAX 11.8 21.5 31.0 40.3 49.1 57.6 65.4 72.7 79.3 85.1 90.2 94.4 97.7 99.7 % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX Max Unit
Note: The Min and Max values are guaranteed by testing the percentage of VSTEPREF that allows the commuatation of the Rsense comparator. IMAX=VSTEPREF/ RSENSE. To obtain the best phase approximation of a sinusoidal wave, the user needs to repeat the final (100%) value. So the full values sequence should be as follows: 0, 1, 2, 3 ... D, E, F, F, F, E, D ... 3, 2, 1, 0. Even if the total spread shows overlapping between current steps, the monotonicity is guaranteed by design.
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When the internal sequencer the minimum angle resolution is nominally 5.625, so depending on the control mode chosen, the selectable steps are the following: Table 40. Internal sequencer
Control mode Typical output current (% of IMAX ) 1/8 step 1/16 step Resulting electrical angle Electrical degrees 45 50.6 56.2 61.9 67.5 73.1 78.8 84.4 90 95.6 101.2 106.9 112.5 118.1 123.8 129.4 135 140.6 146.2 151.9 157.5 163.1 168.8 174.4 180 185.6 191.2 196.9
Half step 1
Full step (2 phases on) 1
Full step (1 phase on)
1/4 step
Phase A (sin)
Phase B (cos) 70.7 63.4 55.6 47.1 38.3 29.0 19.5 9.8 HiZ -9.8 -19.5 -29.0 -38.3 -47.1 -55.6 -63.4 -70.7 -77.3 -83.1 -88.2 -92.4 -95.7 -98.1 -100 -100 -100 -98.1 -95.7
1
1
1 2
70.7 77.3 83.1 88.2 92.4 95.7 98.1 100 100 100 98.1 95.7 92.4 88.2 83.1 77.3 70.7 63.4 55.6 47.1 38.3 29.0 19.5 9.8 HiZ -9.8 -19.5 -29.0
2
3 4
2
3
5 6
4
7 8
2
1
3
5
9 10
6
11 12
4
7
13 14
8
15 16
3
2
5
9
17 18
10
19 20
6
11
21 22
12
23 24
4
2
7
13
25 26
14
27 28
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SABRE-LL-I Table 40. Internal sequencer (continued)
Control mode
Power bridges
Typical output current (% of IMAX ) 1/8 step 1/16 step
Resulting electrical angle Electrical degrees 202.5 208.1 213.8 219.4 225 230.6 236.2 241.9 247.5 253.1 258.8 264.4 270 275.6 281.2 286.9 292.5 298.1 303.8 309.4 315 320.6 326.2 331.9 337.5 343.1 348.8 354.4 360/0 5.6 11.2
Half step
Full step (2 phases on)
Full step (1 phase on)
1/4 step
Phase A (sin)
Phase B (cos) -92.4 -88.2 -83.1 -77.3 -70.7 -63.4 -55.6 -47.1 -38.3 -29.0 -19.5 -9.8 HiZ 9.8 19.5 29.0 38.3 47.1 55.6 63.4 70.7 77.3 83.1 88.2 92.4 95.7 98.1 100 100 100 98.1
8
15
29 30
-38.3 -47.1 -55.6 -63.4 -70.7 -77.3 -83.1 -88.2 -92.4 -95.7 -98.1 -100 -100 -100 -98.1 -95.7 -92.4 -88.2 -83.1 -77.3 -70.7 -63.4 -55.6 -47.1 -38.3 -29.0 -19.5 -9.8 HiZ 9.8 19.5
16 3 5 9 17
31 32 33 34
18
35 36
10
19
37 38
20
39 40
6
3
11
21
41 42
22
43 44
12
23
45 46
24
47 48
7
4
13
25
49 50
26
51 52
14
27
53 54
28
55 56
8
4
15
29
57 58
30
59
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Power bridges Table 40. Internal sequencer (continued)
Control mode Typical output current (% of IMAX ) 1/8 step 1/16 step
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Resulting electrical angle Electrical degrees 16.9 22.5 28.1 33.8 39.4
Half step
Full step (2 phases on)
Full step (1 phase on)
1/4 step
Phase A (sin)
Phase B (cos) 95.7 92.4 88.2 83.1 77.3
60 16 31 61 62 32 63 64
29.0 38.3 47.1 55.6 63.4
The voltage spikes on Rsense could be filtered by selecting an appropriate blanking time on the output of Current sense comparator. The Blanking time selection is made by using the StepBlkTime[1:0] bits in the StpCfg1 register, according to following table: Table 41. Blanking times specification
Blanking time StepBlkTime[1] 0 0 1 1 StepBlkTime[0] Min 0 1 0 1 0.6 0.95 1.5 3 Typ 0.95 1.4 2.25 4.25 Max 1.2 1.85 3 5.5 us us us us Default value Unit Comments
The stepper driver toff time could be programmed by means of the StepOffTime[4:0] bits in StpCfg1 register: Table 42. Stepper off time
Off time StepOffTime[4:0] Typ 0 0 0 00001 00010 00011 00100 00101 00110 00111 01000 2 4 6 8 10 12 14 16 18 us us us us us us us us us Unit
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SABRE-LL-I Table 42. Stepper off time (continued)
Off time StepOffTime[4:0] Typ 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
Power bridges
Unit us us us us us us us us us us us us us us us us us us us us us us us
By means of MixDecPhA[4:0] and MixDecPhB[4:0] in StepCfg2 register, the percentage of Toff time during which each phase will stay in fast decay mode could be programmed according to following table:
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Power bridges Table 43. Stepper fast decay
MixDecPhX[4:0] Fast decay percentage during toff Typ 0 0 0 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 1xxxx 0 6.25 12.5 18.75 25 31.25 37.6 43.75 50 56.25 62.5 68.75 75 81.25 87.5 93.75 100
S ABRE -LL-I
Unit
% % % % % % % % % % % % % % % % %
14.3.6
Synchronous buck regulator configuration
Bridge 3 can be configured to be used as 2 independent synchronous buck regulators or as a single high current synchronous buck regulator using GPIOs pins in order to close the voltage loop. The resulting regulator(s) will implement a non linear, pulse skipping, control loop using an internally generated PWM signal. The voltage will be set externally with a divider network and PWM duty cycle that can be programmed in order to ensure a proper regulation. The regulator will be enabled/disabled using serial interface and will implement a soft start strategy similar to that used by primary switching regulator.
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SABRE-LL-I Here after are summarized the primary features of the regulator(s): Synchronous rectification
Power bridges
Automatic low side disabling when current in the inductance reaches 0 to optimize efficiency at low load Pulse skipping control Internally generated PWM Cycle by cycle current limiting using internal current sensor Protected against load short circuit Soft start circuitry Under voltage signal (both continuous and latched) accessible through serial interface.
Figure 17. Regulator block diagram
V supply
CurrentSense
Charge pump Voltage
High Side Driver
Half Bridge OUT
La Ra
V out
Low Side Driver
From Central Logic
C
Bridge Sense
Voltage Loop Control
Control Logic
Vref=3V N.C. N.C. Vref= 0.8V Regulator Freq
+
GPIO USED as FB
Rb
Regulator Ref
SelFBRef Obtained using spare analog i |
